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FG484 Datasheet(PDF) 140 Page - Microsemi Corporation

Part # FG484
Description  Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology
PDF  212 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

FG484 Datasheet(HTML) 140 Page - Microsemi Corporation

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Military ProASIC3/EL DC and Switching Characteristics
2-126
Revision 3
Table 2-201 • Military ProASIC3/EL CCC/PLL Specification
For Devices Operating at 1.5 V DC Core Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Delay Increments in Programmable Delay Blocks 1, 2
160
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL3
110
MHz
Input cycle-to-cycle jitter (peak magnitude)
1.5
ns
Acquisition Time
LockControl = 0
300
µs
LockControl = 1
6.0
ms
Tracking Jitter4
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1,2
0.6
5.56
ns
Delay Range in Block: Programmable Delay 2 1,2
0.025
5.56
ns
Delay Range in Block: Fixed Delay 1,2
2.2
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max. Peak-to-Peak Period Jitter 5,6
SSO
 2 SSO  4 SSO  8 SSO  16
0.75 MHz to 50 MHz
0.50%
0.50%
0.70%
1.00%
50 MHz to 250 MHz
1.00%
3.00%
5.00%
9.00%
250 MHz to 350 MHz
2.50%
4.00%
6.00%
12.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings.
2. TJ = 25°C, VCC = 1.5 V.
3. Maximum value obtained for a -1 speed grade device in worst-case military conditions. For specific junction temperature
and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
5. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V,
VQ/PQ/TQ type of packages, 20 pF load.
6. Switching I/Os are placed outside of the PLL bank.
Note:
Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.
Figure 2-43 • Peak-to-Peak Jitter Definition
Tperiod_max
Tperiod_min
Output Signal



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