LTC4305CDHD datasheet(10/20 Pages) LINER

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LTC4305

4305f

The LTC4305 is a 2-channel 2-wire bus multiplexer/

switch with bus buffers to provide capacitive isolation

between the upstream bus and downstream buses. Mas-

ters on the upstream 2-wire bus (SDAIN and SCLIN) can

command the LTC4305 to neither, either or both of the 2

downstream buses. Masters can also program the LTC4305

to disconnect the upstream bus from the downstream

buses if the bus is stuck low.

Undervoltage Lockout (UVLO) and ENABLE

Functionality

The LTC4305 contains undervoltage lockout circuitry that

maintains all of its SDA, SCL and ALERT pins in high

impedance states until the device has sufficient VCC sup-

ply voltage to function properly. It also ignores any

attempts to communicate with it via the 2-wire buses in

this condition. When the ENABLE pin voltage is low (below

0.8V), all control bits are reset to their default high

impedance states, and the LTC4305 ignores 2-wire bus

commands. However, with ENABLE low, the LTC4305 still

monitors the ALERT1–ALERT2 pin voltages and pulls the

ALERT pin low if any of ALERT1–ALERT2 is low. When

ENABLE is high, devices can read from and write to the

LTC4305.

Connection Circuitry

Masters on the upstream SDAIN/SCLIN bus can write to

the Bus 1 FET State and Bus 2 FET State bits of register 3

to connect to any combination of downstream channels.

By default, the Connection Circuitry shown in the block

diagram will only connect to downstream channels whose

corresponding Bus Logic State bits in register 3 are high

at the moment that it receives the connection command.

If the LTC4305 is commanded to connect to multiple

channels at once, it will only connect to the channels that

are high. This prevents the master on the upstream bus

from connnecting to a downstream channel that may be

stuck low. Masters can override this feature by setting the

Connection Requirement Bit of register 2 high. With this

bit high, the LTC4305 executes connection commands

without regard to the logic states of the downstream

channels.

Upon receiving the connection command, the Connection

Circuitry shown in the block diagram will activate the

Upstream-Downstream Buffers under two conditions:

first, the master must be commanding connection to one

or more downstream channels, and second, there must be

no stuck low condition (see “Stuck Low Timeout Fault”

discussion that follows). If the connection command is

successful, the Upstream-Downstream Buffer circuitry

passes signals between the upstream bus and the con-

nected downstream buses. The LTC4305 also turns off its

N-channel MOSFET open-drain pull-down on the READY

pin, so that READY can be pulled high by its external pull-

up resistor.

Upstream-Downstream Buffers

Once the Upstream-Downstream Buffers are activated,

the functionality of the SDAIN and any connected down-

stream SDA pins is identical. A low forced on any con-

nected SDA pin at any time results in all pins being low.

External devices must pull the pin voltages below 0.4V

worst-case with respect to the LTC4305’s ground pin to

ensure proper operation. The SDA pins enter a logic high

state only when all devices on all connected SDA pins

force a high. The same is true for SCLIN and the connected

downstream SCL pins. This important feature ensures

that clock stretching, clock arbitration and the acknowl-

edge protocol always work, regardless of the how the

devices in the system are connected to the LTC4305.

The Upstream-Downstream Buffers provide capacitive

isolation between SDAIN/SCLIN and the downstream

connected buses. Note that there is no capacitive isolation

between connected downstream buses; they are only

OPERATIO

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