DM3725CBC datasheet(160/280 Pages) TI

160 / 280 page

DM3730, DM3725

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

www.ti.com

6.4

External Memory Interfaces

The device includes the following external memory interfaces:

•

General-purpose memory controller (GPMC)

•

SDRAM controller (SDRC)

6.4.1

General-Purpose Memory Controller (GPMC)

NOTE

For more information, see Memory Subsystem / General-Purpose Memory Controller section

of the AM/DM37x Multimedia Device Technical Reference Manual (literature number

SPRUGN4).

The GPMC is the unified memory controller used to interface external memory devices such as:

•

Asynchronous SRAM-like memories and ASIC devices

•

Asynchronous page mode and synchronous burst NOR flash

•

NAND flash

6.4.1.1

GPMC/NOR Flash

—Synchronous Mode

Table 6-3 and Table 6-4 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 6-2 through Figure 6-6).

Table 6-2. GPMC/NOR Flash Timing Conditions

—Synchronous Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

1.8

Input signal fall time

1.8

Output Conditions

CLOAD

Output load capacitance(1)

(1) The load setting of the IO buffer: LB0 = 1.

Table 6-3. GPMC/NOR Flash Timing Requirements

—Synchronous Mode(1)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

F12

tsu(dV-clkH)

Setup time, input data gpmc_d[15:0] valid before

2.3

output clock gpmc_clk high

F13

th(clkH-dV)

Hold time, input data gpmc_d[15:0] valid after output

1.5

clock gpmc_clk high

F21

tsu(waitV-clkH)

Setup time, input wait gpmc_waitx(2) valid before

2.3

output clock gpmc_clk high

F22

th(clkH-waitV)

Hold time, input wait gpmc_waitx(2) valid after output

1.9

clock gpmc_clk high

(1) See Section 4.3.4, Processor Clocks.

(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Table 6-4. GPMC/NOR Flash Switching Characteristics

—Synchronous Mode(2) (18)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

1 / tc(clk)

Frequency(15), output clock gpmc_clk

100

MHz

tw(clkH)

Typical pulse duration, output clock gpmc_clk high

0.5P(12)

tw(clkL)

Typical pulse duration, output clock gpmc_clk low

0.5P(12)

160

Timing Requirements and Switching Characteristics

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