DM3725CBC datasheet(169/280 Pages) TI

169 / 280 page

DM3730, DM3725

www.ti.com

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

6.4.1.2

GPMC/NOR Flash

—Asynchronous Mode

Table 6-6 and Table 6-7 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 6-7 through Figure 6-12).

Table 6-5. GPMC/NOR Flash Timing Conditions

—Asynchronous Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

1.8

Input signal fall time

1.8

Output Conditions

CLOAD

Output load capacitance(1)

(1) The load setting of the IO buffer: LB0 = 0.

Table 6-6. GPMC/NOR Flash Internal Timing Parameters

—Asynchronous Mode(1) (2) (4)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

FI1

Delay time, output data gpmc_d[15:0] generation from internal

6.6

7.0

functional clock GPMC_FCLK(3)

FI2

Delay time, input data gpmc_d[15:0] capture from internal functional

4.4

7.0

clock GPMC_FCLK(3)

FI3

Delay time, output chip select gpmc_ncsx generation from internal

6.5

7.0

functional clock GPMC_FCLK(3)

FI4

Delay time, output address gpmc_a[27:1] generation from internal

7.6

7.0

functional clock GPMC_FCLK(3)

FI5

Delay time, output address gpmc_a[27:1] valid from internal functional

7.6

7.0

clock GPMC_FCLK(3)

FI6

Delay time, output lower-byte enable/command latch enable

6.5

7.0

gpmc_nbe0_cle, output upper-byte enable gpmc_nbe1 generation

from internal functional clock GPMC_FCLK(3)

FI7

Delay time, output enable gpmc_noe generation from internal

5.8

7.0

functional clock GPMC_FCLK(3)

FI8

Delay time, output write enable gpmc_nwe generation from internal

7.0

functional clock GPMC_FCLK(3)

FI9

Skew, internal functional clock GPMC_FCLK(3)

100

170

FI10

Delay time, IO direction generation from internal functional clock

6.3

7.0

GPMC_FCLK(3)

(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

(3) GPMC_FCLK is general-purpose memory controller internal functional clock.

(4) See Section 4.3.4, Processor Clocks.

Timing Requirements and Switching Characteristics

169

Submit Documentation Feedback

Product Folder Link(s): DM3730 DM3725

DM3725CBC Datasheet(PDF) 169 Page - Texas Instruments

DM3725CBC Datasheet(HTML) 169 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL