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DM3725CBC Datasheet(PDF) 171 Page - Texas Instruments

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Part # DM3725CBC
Description  Digital Media Processors
PDF  280 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM3725CBC Datasheet(HTML) 171 Page - Texas Instruments

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DM3730, DM3725
www.ti.com
SPRS685D
– AUGUST 2010 – REVISED JULY 2011
Table 6-8. GPMC/NOR Flash Switching Characteristics
—Asynchronous Mode(16) (continued)
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
FA16
tw(aIV)
Pulse durationm output address gpmc_a[26:1]
G(7)
G(7)
ns
invalid between 2 successive R/W accesses
FA18
td(ncsV-noeIV)
Delay time, output chip select gpmc_ncsx(13)
I(8)
– 0.2
I(8) + 2.0
I(8)
– 0.2
I(8) + 2.6
ns
valid to output enable gpmc_noe invalid (Burst
read)
FA20
tw(aV)
Pulse duration, output address gpmc_a[27:1]
D(4)
D(4)
ns
valid
– 2nd, 3rd, and 4th accesses
FA25
td(ncsV-nweV)
Delay time, output chip select gpmc_ncsx(13)
E(5)
– 0.2
E(5) + 2.0
E(5)
– 0.2
E(5) + 2.6
ns
valid to output write enable gpmc_nwe valid
FA27
td(ncsV-nweIV)
Delay time, output chip select gpmc_ncsx(13)
F(6)
– 0.2
F(6) + 2.0
F(6)
– 0.2
F(6) + 2.6
ns
valid to output write enable gpmc_nwe invalid
FA28
td(nweV-dV)
Delay time, output write enable gpmc_ nwe
2.0
2.6
ns
valid to output data gpmc_d[15:0] valid
FA29
td(dV-ncsV)
Delay time, output data gpmc_d[15:0] valid to
J(9)
– 0.2
J(9) + 2.0
J(9)
– 0.2
J(9) + 2.6
ns
output chip select gpmc_ncsx(13) valid
FA37
td(noeV-aIV)
Delay time, output enable gpmc_noe valid to
2.0
2.6
ns
output address gpmc_a[16:1]_d[15:0] phase
end
(1) For single read: A = (CSRdOffTime
– CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)
For single write: A = (CSWrOffTime
– CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)
For burst read: A = (CSRdOffTime
– CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)
For burst write: A = (CSWrOffTime
– CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *
GPMC_FCLK(15)
For writing: B = ((ADVWrOffTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *
GPMC_FCLK(15)
(3) C = ((OEOffTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)
(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(15)
(5) E = ((WEOnTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)
(6) F = ((WEOffTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)
(7) G = Cycle2CycleDelay * GPMC_FCLK(15)
(8) I = ((OEOffTime + (n
– 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *
GPMC_FCLK(15)
(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK(15)
(10) K = ((ADVOnTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)
(11) L = ((OEOnTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)
(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(15)
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(15)
For burst read: N = (RdCycleTime + (n
– 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)
For burst write: N = (WrCycleTime + (n
– 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
(14) M = ((RdCycleTime
– CSOnTime) * (TimeParaGranularity + 1) – 0.5 * CSExtraDelay) * GPMC_FCLK(15)
Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both
RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses
performed to Memory and multiplexed or nonmultiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR
behaviour is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the AM/DM37x Multimedia
Device Technical Reference Manual (literature number SPRUGN4).
(15) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(16) See Section 4.3.4, Processor Clocks.
Copyright
© 2010–2011, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
171
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Product Folder Link(s): DM3730 DM3725



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