DM3725CBC datasheet(178/280 Pages) TI

178 / 280 page

DM3730, DM3725

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

www.ti.com

6.4.1.3

GPMC/NAND Flash

—Asynchronous Mode

Table 6-10 and Table 6-11 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 6-13 through Figure 6-16).

Table 6-9. GPMC/NAND Flash Timing Conditions

—Asynchronous Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

1.8

Input signal fall time

1.8

Output Conditions

CLOAD

Output load capacitance(1)

(1) The load setting of the IO buffer: LB0 = 0.

Table 6-10. GPMC/NAND Flash Internal Timing Parameters

—Asynchronous Mode(1) (2) (4)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

GNFI1

Delay time, output data gpmc_d[15:0] generation from internal

6.5

9.1

functional clock GPMC_FCLK(3)

GNFI2

Delay time, input data gpmc_d[15:0] capture from internal

4.0

5.6

functional clock GPMC_FCLK(3)

GNFI3

Delay time, output chip select gpmc_ncsx generation from

6.5

9.1

internal functional clock GPMC_FCLK(3)

GNFI4

Delay time, output address valid/address latch enable

6.5

9.1

gpmc_nadv_ale generation from internal functional clock

GPMC_FCLK(3)

GNFI5

Delay time, output lower-byte enable/command latch enable

6.5

9.1

gpmc_nbe0_cle generation from internal functional clock

GPMC_FCLK(3)

GNFI6

Delay time, output enable gpmc_noe generation from internal

6.5

9.1

functional clock GPMC_FCLK(3)

GNFI7

Delay time, output write enable gpmc_nwe generation from

6.5

9.1

internal functional clock GPMC_FCLK(3)

GNFI8

Skew, functional clock GPMC_FCLK(3)

100

170

(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

(3) GPMC_FCLK is general-purpose memory controller internal functional clock.

(4) See Section 4.3.4, Processor Clocks.

Table 6-11. GPMC/NAND Flash Timing Requirements

—Asynchronous Mode(4)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

GNF12(1)

tacc(d)

Access time, input data gpmc_d[15:0]

J(2)

(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) J = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(3)

(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(4) See Section 4.3.4, Processor Clocks.

178

Timing Requirements and Switching Characteristics

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