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DM3725CBC Datasheet(PDF) 199 Page - Texas Instruments |
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DM3725CBC Datasheet(HTML) 199 Page - Texas Instruments |
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199 / 280 page  cam_xclki cam_pclk cam_vs cam_hs cam_d[11:0] cam_wen cam_fld FRAME(0) L(0) L(0) D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(2) D(n-1) PAIR IMPAIR ISP16 ISP16 ISP17 ISP18 ISP27 ISP19 ISP21 ISP22 ISP23 ISP20 ISP28 ISP25 ISP26 SWPS038-052 FRAME(0) L(n-1) ISP18 ISP15 ISP24 DM3730, DM3725 www.ti.com SPRS685D – AUGUST 2010 – REVISED JULY 2011 (1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set. (2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data. (3) When the image sensor has fewer than 12 data lines, it is connected to the lower data lines and the unused lines are grounded. (4) It is possible to shift the data to 0, 2, or 4 data internal lanes. (5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode and cam_d[11:0] in 12-bit mode. (6) Optionally, the data write to memory can be qualified by the external cam_wen signal. (7) The cam_wen signal can be used as an external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) In cam_xclki, i can be equal to a or b. See Table 6-22 for ISP15 and ISP16 parameters. Figure 6-27. CPI —12-bit SYNC Normal Interlaced ModeSection 5.3 Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 199 Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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