DM3725CBC datasheet(197/280 Pages) TI

197 / 280 page

cam_xclki

cam_pclk

cam_vs

cam_hs

cam_d[7:0]

cam_wen

cam_fld

D(0)

D(n-3)

D(n-2)

D(n-1)

D(0)

D(1)

D(n-1)

ISP15

ISP16

ISP3

ISP4

ISP5

ISP6

ISP7

ISP8

ISP10

ISP4

ISP9

ISP11

ISP12

SWPS038-051

DM3730, DM3725

www.ti.com

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

(1)

The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.

(2)

The image sensor is connected to the lower data lines and the unused lines are grounded. However, it is possible to shift the data to

0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.

(3)

Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a

external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The

polarity of cam_fld is programmable.

(4)

The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to

transfer an YCbCr data stream or compressed stream to memory at very high speed.

(5)

In cam_xclki, i can be equal to a or b. See Table 6-22 for ISP15 and ISP16 parameters.

Figure 6-26. CPI

—8-Bit SYNC Packed Progressive Mode

6.5.1.2.4 CPI

—12-Bit SYNC Normal Interlaced Mode

Table 6-30 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-27).

Table 6-29. CPI Timing Conditions

—12-Bit SYNC Normal Interlaced Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

2.7

Input signal fall time

2.7

Output Condition

CLOAD

Output load capacitance(1)

8.6

(1) The load setting of the IO buffer: LB0 = 1.

Timing Requirements and Switching Characteristics

197

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DM3725CBC Datasheet(PDF) 197 Page - Texas Instruments

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