DM3725CBC datasheet(193/280 Pages) TI

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cam_pclk

cam_vs

cam_hs

cam_d[N:0]

cam_wen

cam_fld

D(n–1)

D(0)

D(n–1)

D(0)

D(n–1)

EVEN

ODD

ISP1

ISP2

ISP4

ISP5

ISP6

ISP7

ISP9

ISP8

ISP10

ISP11

ISP3

ISP12

ISP13

SWPS038-049

D(0)

D(n–1)

DM3730, DM3725

www.ti.com

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

(1)

The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as

an external memory write-enable signal. For further details, see the AM/DM37x Multimedia Device Technical Reference Manual

(literature number SPRUGN4).

(2)

N = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). When the number of data

lines is less than cam_d[N:0], data lines can be connected to the upper or lower lines of cam_d[N:0]. Lines not connected must be

tied low. For more information about video port mapping, see the AM/DM37x Multimedia Device Technical Reference Manual

(literature number SPRUGN4).

Figure 6-24. CPI

—Video and Graphics Digitizer—1.8-V Interlaced Mode

6.5.1.2.2 CPI

—12-Bit SYNC Normal Progressive Mode

Table 6-26 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-25).

Table 6-25. CPI Timing Conditions

—12-Bit SYNC Normal Progressive Mode(1)

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

2.7

Input signal fall time

2.7

Output Condition

CLOAD

Output load capacitance

8.6

(1) The load setting of the IO buffer: LB0 = 1.

Timing Requirements and Switching Characteristics

193

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