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DM3725CBC Datasheet(PDF) 194 Page - Texas Instruments

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Part # DM3725CBC
Description  Digital Media Processors
PDF  280 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM3725CBC Datasheet(HTML) 194 Page - Texas Instruments

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DM3730, DM3725
SPRS685D
– AUGUST 2010 – REVISED JULY 2011
www.ti.com
Table 6-26. CPI Timing Requirements
—12-Bit SYNC Normal Progressive Mode(4) (5)
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
ISP17
1 / tc(pclk)
Frequency(1), input pixel clock cam_pclk
75
45
MHz
ISP18
tw(pclkH)
Typical pulse duration, input pixel clock cam_pclk high
0.5P(2)
0.5P(2)
ns
ISP18
tw(pclkL)
Typical pulse duration, input pixel clock cam_pclk low
0.5P(2)
0.5P(2)
ns
tdc(pclk)
Duty cycle error, input pixel clock cam_pclk
0.5P(2) -
0.5P(2) -
ns
3.465
6.93
tJ(pclk)
Cycle jitter(3), input pixel clock cam_pclk
0.0649*P
0.0649*P
ns
(2)
(2)
ISP19
tsu(dV-pclkH)
Setup time, input data cam_d[11:0] valid before input
1.82
3.25
ns
pixel clock cam_pclk rising edge
ISP20
th(pclkH-dV)
Hold time, input data cam_d[11:0] valid after input
1.82
3.25
ns
pixel clock cam_pclk rising edge
ISP21
tsu(dV-vsH)
Setup time, input vertical synchronization cam_vs valid
1.82
3.25
ns
before input pixel clock cam_pclk rising edge
ISP22
th(pclkH-vsV)
Hold time, input vertical synchronization cam_vs valid
1.82
3.25
ns
after input pixel clock cam_pclk rising edge
ISP23
tsu(dV-hsH)
Setup time, input horizontal synchronization cam_hs
1.82
3.25
ns
valid before input pixel clock cam_pclk rising edge
ISP24
th(pclkH-hsV)
Hold time, input horizontal synchronization cam_hs
1.82
3.25
ns
valid after input pixel clock cam_pclk rising edge
ISP25
tsu(dV-hsH)
Setup time, input write enable cam_wen valid before
1.82
3.25
ns
input pixel clock cam_pclk rising edge
ISP26
th(pclkH-hsV)
Hold time, input write enable cam_wen valid after input
1.82
3.25
ns
pixel clock cam_pclk rising edge
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_pclk period in ns
(3) Maximum cycle jitter supported by cam_pclk input clock.
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.
(5) See Section 4.3.4, Processor Clocks.
194
Timing Requirements and Switching Characteristics
Copyright
© 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): DM3730 DM3725



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