| Electronic Components Datasheet Search |
|
ADS1274IPAPR Datasheet(PDF) 33 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADS1274IPAPR Datasheet(HTML) 33 Page - Texas Instruments |
|
33 / 51 page ![]() CH1 DOUT1 CH2 DOUT2 CH3 DOUT3 CH4 DOUT4 SCLK DRDY (SPI) FSYNC (Frame-Sync) 1 2 22 23 24 CH5 DOUT5 CH6 DOUT6 CH7 DOUT7 CH8 DOUT8 ADS1278 Only 25 26 ADS1274 ADS1278 www.ti.com SBAS367F – JUNE 2007 – REVISED FEBRUARY 2011 Figure 80. Discrete Data Output Mode Table 15. Maximum Channels in a Daisy-Chain DAISY-CHAINING (fSCLK = fCLK) Multiple ADS1274/78s can be daisy-chained together MAXIMUM NUMBER to output data on a single pin. The DOUT1 data MODE SELECTION CLKDIV OF CHANNELS output pin of one device is connected to the DIN of High-Speed 1 10 the next device. As shown in Figure 81, the DOUT1 High-Resolution 1 21 pin of device 1 provides the output data to a controller, and the DIN of device 2 is grounded. 1 21 Low-Power Figure 82 shows the data format when reading back 0 10 data. 1 106 Low-Speed The maximum number of channels that may be 0 21 daisy-chained in this way is limited by the frequency of fSCLK, the mode selection, and the CLKDIV input. Whether the interface protocol is SPI or Frame-Sync, The frequency of fSCLK must be high enough to it is recommended to synchronize all devices by tying completely shift the data out from all channels within the SYNC inputs together. When synchronized in SPI one fDATA period. Table 15 lists the maximum number protocol, it is only necessary to monitor the DRDY of daisy-chained channels when fSCLK = fCLK. output of one ADS1274/78. To increase the number of data channels possible in In Frame-Sync interface protocol, the data from all a chain, a segmented DOUT scheme may be used, devices are ready after the rising edge of FSYNC. producing two data streams. Figure 83 illustrates four Since DOUT1 and DIN are both shifted on the falling ADS1274/78s, with pairs of ADS1274/78s edge of SCLK, the propagation delay on DOUT1 daisy-chained together. The channel data of each creates a setup time on DIN. Minimize the skew in daisy-chained pair are shifted out in parallel and SCLK to avoid timing violations. received by the processor through independent data channels. © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Link(s): ADS1274 ADS1278 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |