APW8821 datasheet(14/24 Pages) ANPEC

14 / 24 page

Rev. A.1 - Feb., 2011

APW8821

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Function Description (Cont.)

Digital Soft-Start

Power OK Indicator

The APW8821 integrates digital soft-start circuits to ramp

up the output voltage of the converter to the programmed

regulation setpoint at a predictable slew rate. The slew

rate of output voltage is internally controlled to limit the

inrush current through the output capacitors during soft-

start process. The figure 1 shows soft-start sequence.

When the REFIN pin is pulled above the rising EN

threshold voltage, the V

OCSET voltage is equal to 10µA x

OCSET. When VCC rising POR threshold is triggered, the

device starts to sample and hold the current-limit setting

threshold. The maximum sample time is 650us, so user

must make sure that V

OCSET reaches set up value cor-

rectly during this time.

During soft-start stage before the POK pin is ready, the

under-voltage protection is prohibited. The over-voltage

and over-current protection functions are enabled. If the

output capacitor has residue voltage before start-up, both

low-side and high-side MOSFETs are in off-state until the

internal digital soft-start voltage is equal to the V

FB voltage.

This will ensure that the output voltage starts from its

existing voltage level.

In the event of under-voltage or shutdown, the chip en-

ables the soft-stop function. The soft-stop function dis-

charges the output voltages to the GND through an inter-

nal 20

Ω switch. Cycling the REFIN enable signal or VCC

power-on-reset signal can reset the latch.

Figure 1. Soft-Start Sequence

The APW8821 features an open-drain POK pin to indi-

cate output regulation status. In normal operation, when

the output voltage rises above 90% of its target value, the

POK goes high. When the output voltage returns 90% or

outruns 125% of the target voltage, POK signal will be

pulled low after 30 us noise filter. it is a latch operation.

Since the FB pin is used for both feedback and monitor-

ing purposes, the output voltage deviation can be coupled

directly to the FB pin by the capacitor in parallel with the

voltage divider as shown in the typical applications. In

order to prevent false POK from dropping, capacitors need

to parallel at the output to confine the voltage deviation

with severe load step transient and the POK comparator

has a built-in 30

µs noise filter.

from

When current-limit setting action has finished, the device

initiates a soft-start process to ramp up the output voltage.

The soft-start interval, T

SS, is about 1ms (typical value).

Under-Voltage Protection (UVP)

In the operational process, if a short-circuit occurs, the

output voltage will drop quickly. When load current is big-

ger than current-limit threshold value, the output voltage

will fall out of the required regulation range. The under-

voltage protection circuit continually monitors the V

FB af-

ter soft-start is completed. If a load step is strong enough

to pull the output voltage lower than the under-voltage

threshold, the device starts to soft-stop process to shut

down the output gradually. The under-voltage threshold

is 70% of the normal output voltage. The under-voltage

comparator has a built-in 2

µs noise filter to prevent the

chip from wrong UVP shutdown caused by noise. Cy-

cling the REFIN enable signal or VCC power-on-reset

signal can reset the latch.

TSS = t2-t1 = 1ms

VOUT

VCC

VPOK

95% x VREF

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