DSPIC30F4012 datasheet(128/236 Pages) MICROCHIP

128 / 236 page

dsPIC30F4011/4012

DS70135E-page 126

19.4

Message Reception

19.4.1

RECEIVE BUFFERS

The CAN bus module has 3 receive buffers. However,

one of the receive buffers is always committed to mon-

itoring the bus for incoming messages. This buffer is

called the message assembly buffer (MAB). There are

two receive buffers, visibly denoted as RXB0 and

RXB1, that can essentially instantaneously receive a

complete message from the protocol engine.

All messages are assembled by the MAB, and are

transferred to the RXBn buffers only if the acceptance

filter criterion is met. When a message is received, the

RXxIF flag (C1INTF<0> or C1INIF<1>) will be set. This

bit can only be set by the module when a message is

received. The bit is cleared by the CPU when it has

completed processing the message in the buffer. If the

RXxIE bit (C1INTE<0> or C1INTE<1>) is set, an

interrupt will be generated when a message is

received.

RXF0 and RXF1 filters with the RXM0 mask are

associated with RXB0. The filters, RXF2, RXF3, RXF4

and RXF5, and the mask, RXM1, are associated with

RXB1.

19.4.2

MESSAGE ACCEPTANCE FILTERS

The message acceptance filters and masks are used to

determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers. Once a valid message has been received into the

Message Assembly Buffer (MAB), the identifier fields of

the message are compared to the filter values. If there

is a match, that message will be loaded into the

appropriate receive buffer.

The acceptance filter looks at incoming messages for

the RXIDE bit (CiRXnSID<0>) to determine how to

compare the identifiers. If the RXIDE bit is clear, the

message is a standard frame and only filters with the

EXIDE bit (C1RXFxSID<0>) clear are compared. If the

RXIDE bit is set, the message is an extended frame

and only filters with the EXIDE bit set are compared.

19.4.3

MESSAGE ACCEPTANCE FILTER

MASKS

The mask bits essentially determine which bits to apply

the filter to. If any mask bit is set to a zero, then that bit

will automatically be accepted regardless of the filter

bit. There are 2 programmable acceptance filter masks

associated with the receive buffers, one for each buffer.

19.4.4

RECEIVE OVERRUN

An overrun condition occurs when the Message

Assembly Buffer (MAB) has assembled a valid

received message, the message is accepted through

the acceptance filters, and when the receive buffer

associated with the filter has not been designated as

clear of the previous message.

The overrun error flag, RXxOVR (C1INTF<15> or

C1INTF<14>) and the ERRIF bit (C1INTF<5>) will be

set and the message in the MAB will be discarded.

If the DBEN bit is clear, RXB1 and RXB0 operate inde-

pendently. When this is the case, a message intended

for RXB0 will not be diverted into RXB1 if RXB0

contains an unread message and the RX0OVR bit will

be set.

If the DBEN bit is set, the overrun for RXB0 is handled

differently. If a valid message is received for RXB0 and

RXFUL = 1, it indicates that RXB0 is full and

RXFUL = 0 indicates that RXB1 is empty, the message

for RXB0 will be loaded into RXB1. An overrun error will

not be generated for RXB0. If a valid message is

received for RXB0 and RXFUL = 1, and RXFUL = 1

indicates that both RXB0 and RXB1 are full, the

message will be lost and an overrun will be indicated

for RXB1.

19.4.5

RECEIVE ERRORS

The CAN module will detect the following receive

errors:

• Cyclic Redundancy Check (CRC) Error

• Bit Stuffing Error

• Invalid Message Receive Error

These receive errors do not generate an interrupt.

However, the receive error counter is incremented by

one in case one of these errors occur. The RXWAR bit

(C1INTF<9>) indicates that the receive error counter

has reached the CPU warning limit of 96 and an

interrupt is generated.

19.4.6

RECEIVE INTERRUPTS

Receive interrupts can be divided into 3 major groups,

each including various conditions that generate

interrupts:

19.4.6.1

Receive Interrupt

A message has been successfully received and loaded

into one of the receive buffers. This interrupt is acti-

vated immediately after receiving the End-of-Frame

(EOF) field. Reading the RXxIF flag will indicate which

receive buffer caused the interrupt.

19.4.6.2

Wake-up Interrupt

The CAN module has woken up from Disable mode or

the device has woken up from Sleep mode.

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