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AM28F256 Datasheet(PDF) 27 Page - Advanced Micro Devices

Part # AM28F256
Description  256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
PDF  35 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM28F256 Datasheet(HTML) 27 Page - Advanced Micro Devices

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Am28F256
27
AC Characteristics—Write/Erase/Program Operations
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.
3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
4. Not 100% tested.
Parameter Symbols
Parameter Description
Am28F256 Speed Options
Unit
JEDEC
Standard
-70
-90
-120
-150
-200
tAVAV
tWC
Write Cycle Time (Note 4)
Min
70
90
120
150
200
ns
tAVWL
tAS
Address Set-up Time
Min
0
0
0
0
0
ns
tWLAX
tAH
Address Hold Time
Min
4545
5060
75
ns
tDVWH
tDS
Data Setup Time
Min
45
45
50
50
50
ns
tWHDX
tDH
Data Hold Time
Min
10
10
10
10
10
ns
tWHGL
tWR
Write Recovery Time
before Read
Min
6
6
666
µs
tGHWL
Read Recovery Time
before Write
Min
0
0
000
µs
tELWL
tCS
Chip Enable Set-up Time
Min
0
0
0
0
0
ns
tWHEH
tCH
Chip Enable Hold Time
Min
0
0
0
0
0
ns
tWLWH
tWP
Write Pulse Width
Min
45
45
50
60
60
ns
tWHWL
tWPH
Write Pulse
Width HIGH
Min
2020
2020
20
ns
tWHWH1
Duration of Programming
Operation (Note 2)
Min
1010
1010
10
µs
tWHWH2
Duration of
Erase Operation (Note 2)
Min
9.5
9.5
9.5
9.5
9.5
ms
tVPEL
VPP Setup Time to
Chip Enable LOW (Note 4)
Min
100
100
100
100
100
ns
tVCS
VCC Set-up Time to
Chip Enable LOW (Note 4)
Min
5050
5050
50
µs
tVPPR
VPP Rise Time
90% VPPH (Note 4)
Min
500
500
500
500
500
ns
tVPPF
VPP Fall Time
10% VPPL (Note 4)
Min
500
500
500
500
500
ns
tLKO
VCC < VLKO
to Reset (Note 4)
Min
100
100
100
100
100
ns



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