AM79C32AVC datasheet(58/101 Pages) AMD

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Am79C30A/32A Data Sheet

the data output pin (SBOUT) is also forced to High-Z

(seen as a High on the system bus due to the external

pullup resistor), and the Am79C30A begins monitoring

the data input pin (SBIN) for the presence of a timing

request from any downstream units.

Activation

Activation can be initiated locally by the processor or re-

motely by one of the downstream units. To activate lo-

cally, the processor sets the activation/deactivation bit in

PPCR1 (starting the clocks), and then proceeds through

the software activation protocol on the C/Ichannel. For

remote activation, the upstream device receives a re-

quest from the downstream device via the data input pin.

When the data input pin (SBIN) goes Low, Am79C30A

will generate an IOM-2 timing-request interrupt, bit 6 in

the Peripheral Port Status Register (PPSR). The proces-

sor must respond to this interrupt, and restart the IOM-2

clocks by setting the activation/deactivation bit in

PPCR1. Once the clocks are running, the downstream

device can request full activation via the C/I channel

using the IOM-2 software protocol.

DSC/IDC Circuit as a Downstream Device

(Clock Slave)

Deactivation

Deactivation is normally initiated by the upstream de-

vice as described above. When the deactivation re-

quest is received by the downstream device over the

C/I channel, the processor must respond by sending

the deactivation indication over the C/I channel. The

upstream device will then send the deactivation confir-

mation command over the C/I channel and stop the

IOM-2 clocks. The Am79C30A will detect that the clock

has stopped (defined as no clock pulse received for

650 ns) and force itself to the deactivated state. In the

deactivated state, SBIN, and SBOUT are both forced to

a High-Z state, and the SCLK input is monitored for any

rising edge that would indicate an activation request

from the upstream device.

Activation

Once again, activation can originate from either the up-

stream or the downstream device. To activate the inter-

face from the downstream device, the processor sets

the activation/deactivation bit in the PPCR1 register.

This will force the Am79C30A to pull its data output pin

(SBIN in this case, since the I/O pin definition is re-

versed when talking to the upstream device) Low,

causing the upstream device to start the IOM-2 clocks.

Once the clocks are running, as indicated by SCLK

input going High, the Am79C30A will generate an

IOM-2 timing request interrupt (bit 6 in PPSR). The pro-

cessor must respond to the interrupt by loading the

proper C/I command response into C/ITRDO, then

clearing the activation/deactivation bit in PPCR1. This

will release the data output pin (SBIN) from being held

Low and allow the processor to complete the activation

procedure by sending the proper commands over the

C/I channel.

When the activation is originated from the upstream

device, the Am79C30A will generate an IOM-2 timing

request interrupt (bit 6 in PPSR) when the IOM-2clocks

become active as indicated by the SCLK input pin

going High. The Am79C30A will begin normal IOM-2

transmission/reception as soon as SCLK appears; no

intervention from the microprocessor is required. How-

ever, the processor must respond to the interrupt and

perform the normal C/I channel software handshakes

before activation will be complete.

TIC Bus Operation

C/I0 Channel Arbitration

Software control for the IOM-2 Bus Accessed (BAC) bit

will be added at bit 7 of CITDR0, which is currently re-

served. It will be referred to as the BAR, “Bus Access

Request” bit. This bit will be used to gain access to the

C/I0 channel when TIC bus supp or t is enabl ed

(PPCR3.3=1). The BAR bit should be set whenever the

DSC has C/I0 data available to transmit. When

CITDR0.7=1, the TIC bus will arbitrate access to the

C/I0 channel with other devices on the IOM-2 interface

using the TIC address programmed into PPCR3.2–0.

The TIC bus control logic will check to see if the BAC

bit on the line is 0 or 1 to determine if another down-

stream device currently owns the bus. If zero, the DSC

will wait. Once a one is detected in BAC, the logic will

place the DSC's TIC bus address on the open drain

output. It will then sample this output with the IOM-2 re-

ceived data strobe timing to check for conflict with other

downstream devices. If the received TIC address and

the contents of PPCR3.2–0 match, the logic will set the

BAC output to “0” indicating to other downstream de-

vices that the DSC has taken control of the D and C/I0

channels.

After it sets its BAC output to 0, the logic will compare

the TIC address on the line with PPCR3.2–0 in one

more frame to ensure ownership of the bus. If a mis-

compare occurs, the DSC will set its BAC output to 1

and return to the beginning of arbitration.

Once access is gained, the D and C/I0 channels are

the possession of the DSC. This allows the DSC to

complete C/I0 communication with the Layer 1 device

without interruption from other downstream devices.

(Since the TIC bus is used for arbitration of both D and

C/I0 channel communication, gaining access for one

implicitly gives you access to the other). After the DSC

completes C/I0 communication, software should set

CITDR0.7=0 to allow other downstream devices ac-

cess to the D and C/I0 channels. The logic will set the

BAC bit output of the DSC back to 1, as long as the

AM79C32AVC Datasheet(PDF) 58 Page - Advanced Micro Devices

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