AM79C970AVCW datasheet(53/219 Pages) AMD

53 / 219 page

P R E L I M I N A R Y

AMD

Am79C970A

Master Abort

The PCnet-PCI II controller will terminate its cycle with a

Master Abort sequence if

DEVSEL is not asserted within

4 clocks after

FRAME is asserted. Master Abort is

treated as a fatal error by the PCnet-PCI II controller.

The PCnet-PCI II controller will reset all CSR locations

to their STOP_RESET values. The BCR and PCI con-

figuration registers will not be cleared. Any on-going net-

work transmission is terminated in an orderly sequence.

If less than 512 bits have been transmitted onto the net-

work, the transmission will be terminated immediately,

generating a runt packet. If 512 bits or more have been

transmitted, the message will have the current FCS

inverted and appended at the next byte boundary to

guarantee

FCS

error

detected

the

receiving station.

RMABORT (in the PCI Status register, bit 13) will be set

to indicate that the PCnet-PCI II controller has termi-

nated its transaction with a master abort. In addition,

SINT (CSR5, bit 11) will be set to ONE. When SINT is

set,

INTA is asserted if the enable bit SINTE (CSR5, bit

10) is set to ONE. This mechanism can be used to in-

form the driver of the system error. The host can read

the PCI Status register to determine the exact cause

of the interrupt.

19436A-25

FRAME

CLK

IRDY

TRDY

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

234

DATA

PAR

REQ

GNT

0000

Figure 22. Master Abort

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