TAS5719PHPR datasheet(21/68 Pages) TI

21 / 68 page

TAS5717

TAS5719

www.ti.com

SLOS655A

– NOVEMBER 2010 – REVISED FEBRUARY 2011

Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5717/9 fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the PVDD and AVDD supply voltages reach 4.5 V and 2.7 V, respectively. Although PVDD

and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or on either

PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT

being asserted low.

CLOCK, AUTO DETECTION, AND PLL

The TAS5717/9 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the clock control register

The TAS5717/9 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1

× fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock-control logic to the appropriate settings for all supported clock

rates as defined in the clock control register.

TAS5717/9 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)

and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the

system autodetects the new rate and reverts to normal operation. During this process, the default volume is

restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly

(also called soft unmute) as defined in volume register (0x0E).

SERIAL DATA INTERFACE

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5717/9 DAP accepts serial data

in 16-, 20-, or 24-bit left-justified, right-justified, or I2S serial data format.

PWM Section

The TAS5717/9 DAP device uses noise-shaping and sophisticated nonlinear correction algorithms to achieve

high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise

shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from

the DAP and outputs two BTL PWM audio output channels.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1- and 48-kHz are included and can be

enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

For detailed description of using audio processing features like DRC and EQ, see the User's Guide and

TAS570X GDE software development tool documentation. Also see the GDE software development tool for the

device data path.

2C COMPATIBLE SERIAL CONTROL INTERFACE

The TAS5717/9 DAP has an I2C serial control slave interface to receive commands from a system controller. The

serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait

states. As an added feature, this interface operates even if MCLK is absent.

The serial control interface supports both single-byte and multiple-byte read and write operations for status

registers and the general control registers associated with the PWM.

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TAS5719PHPR Datasheet(PDF) 21 Page - Texas Instruments

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