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SC16IS752 Datasheet(PDF) 49 Page - NXP Semiconductors |
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SC16IS752 Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 60 page  SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 9 — 22 March 2012 49 of 60 NXP Semiconductors SC16IS752; SC16IS762 Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 39. SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD =2.5 V 0.2 V, Tamb = 40 Cto+85 C; or VDD =3.3 V 0.3 V, Tamb = 40 Cto +95 C; VIL and VIH refer to input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified. Symbol Parameter Conditions VDD =2.5 V VDD =3.3 V Unit Min Max Min Max tTR CS HIGH to SO 3-state CL = 100 pF - 100 - 100 ns tCSS CS to SCLK setup time 100 - 100 - ns tCSH CS to SCLK hold time 5 - 5 - ns tDO SCLK fall to SO valid delay time CL = 100 pF - 25 - 20 ns tDS SI to SCLK setup time 10 - 10 - ns tDH SI to SCLK hold time 10 - 10 - ns tCP SCLK period tCL + tCH 83 - 67 - ns tCH SCLK HIGH time 30 - 25 - ns tCL SCLK LOW time 30 - 25 - ns tCSW CS HIGH pulse width 200 - 200 - ns td9 SPI output data valid time 200 - 200 - ns td10 SPI modem output data valid time 200 - 200 - ns td11 SPI transmit interrupt clear time 200 - 200 - ns td12 SPI modem input interrupt clear time 200 - 200 - ns td13 SPI interrupt clear time 200 - 200 - ns td14 SPI receive interrupt clear time 200 - 200 - ns tw(rst) reset pulse width 3 - 3 - s Fig 30. Detailed SPI-bus timing tCSH tCSS tCL tCH tCSH tDO tTR tDS tDH SO SI SCLK CS 002aab066 tCSW |
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