SCS750F datasheet(2/5 Pages) MAXWELL

2 / 5 page

SCS750

mICroeLeCtroNICS

page 2 of 5

| Doc. # 1004741 | Rev.

PPC

750FX

Memory Controllers,

Timers (3), Interrupts,

DMA (3), UART's (2)

Watchdog Timer

Mission Timer

PPC

750FX

PPC

750FX

SDRAM Interface

Double Device

Correction Reed-

Solomon

EEPROM

Interface

SEC/DED EDAC

7.0MB User EEPROM

SDRAM

256 MBytes

0.5MB Secondary SuROM

0.5MB Primary SuROM

PCI Target

PCI-PCI

Bridge

LOCAL PCI BUS (32 bit, 33MHz)

Actel RT-AXS

SEU Immune FPGA

Actel RT-AXS SEU Immune FPGA

MIL-STD-

1553

BC/RT/MT

Rad-Hard

(Optional)

Power Input: 3.3V / 5V

(3) Timer Synch# Signals (input/output) [J3 Connector]

Synch/Asynch

Serial

Communications

Controller (SCC)

(2)

GPIO

General

Purpose I/O

Controller

(32 I/O's)

System

Timers

32 Bit

(4 Timers)

count-

down

1553

Interface

Logic

3.3V CMOS, 16 Discretes shared with Backplane

3.3V CMOS, 32 Discretes [J3/J5 Connectors]

LVDS Standard, RS-422 Option [J3 Connector]

JTAG/PowerPC ICE

CPU Error (3)

Voltage Sense Output

UART0 (LVDS/RS422)

FLIGHT/FLIGHT#

Inject PPC Errors (3)

FT_RESET#

Main Memory

Arbiters 8 channel arbiter

80 MHz

Oscillator

To FPGA's,

PPC's, SDRAM's

cPCI Bus, 3.3V

32 bit, 33MHz

PCI

Master

PCI

Target

System Controller Chip

PCI-IF Chip

EEPROM Write Enable (3)

[J3 Connector]

FP_RESET#

FP_HALT#

XFMR

Up to 800MHz

>1,800 MIPS

40MHz Clock

Distribution

FPGA Silicon Expl.

WD_DISABLE#

60X Master

Bus Snooping

PCI (8)

cPCI (8)

33MHz Clock

Distribution

SuROM/EEPROM

Write enables

Power

Switch

DC/DC

FPGA

Core

3.3V

1.5V

Local PCI to J4

2.5V I/O

Regulator

3.3V

2.5V - PPC

I/O Voltages

DC/DC

Converter

66 MHz

Oscillator

RAD Hard

1553 SRAM

XFMR

Set

Voltage

UART0 (LVDS/RS422)

UART(0/1) - 2 channel (LVDS/RS422)

Auto Controller/Peripheral Configuration

Cold Sparing Capable

Processor & SDRAM Error Logging

Front Panel Test Connector

Front Panel Flight Connector

Single Event Upset Mitigation

SCS750

Enhanced Features

100 Years

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