MPC8347VRAGDB datasheet(20/99 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

DDR and DDR2 SDRAM

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 20 shows the DDR and DDR2 output AC timing specifications.

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (PBGA

package)

tMCK

5—

MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (TBGA

package)

tMCK

7.5

—

ADDR/CMD/MODT output setup with respect to MCK

tDDKHAS

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

ADDR/CMD/MODT output hold with respect to MCK

tDDKHAX

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

MCS(n) output setup with respect to MCK

tDDKHCS

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

MCS(n) output hold with respect to MCK

tDDKHCX

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

MCK to MDQS Skew

tDDKHMH

–0.6

0.6

MDQ/MECC/MDM output setup with respect to

MDQS

tDDKHDS,

tDDKLDS

400 MHz

700

—

333 MHz

775

—

266 MHz

1100

—

200 MHz

1200

—

MDQ/MECC/MDM output hold with respect to MDQS

tDDKHDX,

tDDKLDX

400 MHz

700

—

333 MHz

900

—

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