PIC16F84A datasheet(136/337 Pages) MICROCHIP

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PIC16C6X

DS30234D-page 136

13.5

Interrupts

The PIC16C6X family has up to 11 sources of interrupt.

The interrupt control register (INTCON) records individ-

ual interrupt requests in ﬂag bits. It also has individual

and global interrupt enable bits.

Global interrupt enable bit, GIE (INTCON<7>) enables

(if set) all un-masked interrupts or disables (if cleared)

all interrupts. When bit GIE is enabled, and an interrupt

ﬂag bit and mask bit are set, the interrupt will vector

immediately. Individual interrupts can be disabled

through their corresponding enable bits in the INTCON

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enable interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overﬂow interrupt ﬂag bits are contained

in the INTCON register.

The peripheral interrupt ﬂag bits are contained in spe-

cial function registers PIR1 and PIR2. The correspond-

ing interrupt enable bits are contained in special

function registers PIE1 and PIE2 and the peripheral

interrupt enable bit is contained in special function reg-

ister INTCON.

When an interrupt is responded to, bit GIE is cleared to

disable any further interrupts, the return address is

pushed onto the stack and the PC is loaded with

0004h. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the RB0/INT pin

or RB port change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs

(Figure 13-

19). The latency is the same for one or two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding

mask bit or global enable bit, GIE.

avoid inﬁnite interrupt requests. Individual interrupt ﬂag

bits are set regardless of the status of their correspond-

ing mask bit or the GIE bit.

Note:

For the PIC16C61/62/64/65, if an interrupt

occurs while the Global Interrupt Enable

bit, GIE is being cleared, bit GIE may unin-

tentionally be re-enabled by the user’s

Interrupt Service Routine (the RETFIE

instruction). The events that would cause

this to occur are:

An instruction clears the GIE bit while

an interrupt is acknowledged

The program branches to the Interrupt

vector and executes the Interrupt Ser-

vice Routine.

The Interrupt Service Routine com-

pletes with the execution of the RET-

FIE

instruction. This causes the GIE

bit to be set (enables interrupts), and

the program returns to the instruction

after the one which was meant to dis-

able interrupts.

Perform the following to ensure that

interrupts are globally disabled.

LOOP BCF INTCON,GIE

;Disable Global

;Interrupt bit

BTFSC INTCON,GIE

;Global Interrupt

;Disabled?

GOTO

LOOP

;NO, try again

;Yes, continue

;with program flow

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