PIC16F84A datasheet(141/337 Pages) MICROCHIP

141 / 337 page

DS30234D-page 141

PIC16C6X

13.8

Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, status bit PD (STATUS<3>) is cleared,

status bit TO (STATUS<4>) is set, and the oscillator

driver is turned off. The I/O ports maintain the status

they had before the SLEEP instruction was executed

(driving high, low, or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, and disable

external clocks. Pull all I/O pins, that are hi-impedance

inputs, high or low externally to avoid switching cur-

rents caused by ﬂoating inputs. The T0CKI input should

also be at VDD or VSS for lowest current consumption.

The contribution from on-chip pull-ups on PORTB

should be considered.

The MCLR/VPP pin must be at a logic high level

(VIHMC).

13.8.1

WAKE-UP FROM SLEEP

The device can wake from SLEEP through one of the

following events:

External reset input on MCLR/VPP pin.

Watchdog

Timer

Wake-up

(if

WDT

was

enabled).

Interrupt from RB0/INT pin, RB port change, or

some peripheral interrupts.

External MCLR Reset will cause a device reset. All

other events are considered a continuation of program

execution and cause a “wake-up”. The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up is cleared when SLEEP is invoked. The TO bit

is cleared if WDT time-out occurred (and caused wake-

up).

The following peripheral interrupts can wake the device

from SLEEP:

TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

SSP (Start/Stop) bit detect interrupt.

SSP transmit or receive in slave mode (SPI/I2C).

CCP capture mode interrupt.

Parallel Slave Port read or write.

USART TX or RX (synchronous slave mode).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Other peripherals can not generate interrupts since

during SLEEP, no on-chip Q clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOP after the SLEEP instruction.

13.8.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt ﬂag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP

instruction, the SLEEP instruction will com-

plete as a NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bits will not be cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will imme-

diately wake up from sleep. The SLEEP instruction

will be completely executed before the wake-up.

Therefore, the WDT and WDT postscaler will be

cleared, the TO bit will be set and the PD bit will

be cleared.

Even if the ﬂag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

PIC16F84A Datasheet(PDF) 141 Page - Microchip Technology

PIC16F84A Datasheet(HTML) 141 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL