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AS3658F-BCTP Datasheet(PDF) 98 Page - ams AG

Part # AS3658F-BCTP
Description  Power and Audio Management Unit for Portable Devices
PDF  158 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3658F-BCTP Datasheet(HTML) 98 Page - ams AG

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www.austriamicrosystems.com
Revision 1v13
97 - 157
AS3658
Data Sheet Confidential - Detail ed Descri ption- Audio Functi ons
9.5.1 PCM mode settings
Compatible with BlueCore3-ROM:
Figure 43. Short Frame Sync (shown with 16-bit Sample)
The following setup on PCM-Master side is needed:
AS3658 is slave only
PCM_SYNC is in short frame mode
PCM_SYNC rate is 8ksamples/s
PCM_CLK= 512kHz only (64 x PCM_SYNC)
16 Bit Linear coding of PCM_OUT and PCM_IN (MSB first, LSB last)
Mono (single channel) operation only. Only the right channel of the AS3658 is used. The left channel is same as
right channel (in the input direction of AS3658) and has to be ignored by PCM master (in output direction of
AS3658)
Note: Internally the right channel is copied to the right and left channel.
The following setup of AS3658 is needed:
Sclk_invert=1
i2s_mclk_en=0 and mclk_invert=1 (internal PLL used for generation of internal LRCLK)
pcm_mode=1 and ad_fs2=0 (Necessary to allow unsymmetrical LRCLK and sample rate of 8kHz of ADC)
7
pcm_mode
0b
R/W
0
Normal I2S mode
1
PCM mode selected. The following additional
settings are necessary to enable PCM mono
mode:
sclk_invert=1
i2s_mclk_en=0 and mclk_invert=1 (internal PLL
used for generation of internal LRCLK)
Table 100. i2s master control2 Register
Addr:132
I2s master control2
This register controls the external clock divider and modes for i2s master
mode
Bit
Bit Name
Default Access
Description
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
In short Frame Sync the falling edge of PCM_SYNC indicate the start of the PCM word. PCM_Sync is always one clock cycle long.
PCM_SYNC
PCM_CLK
PCM_OUT
Undefined
Undefined
PCM_IN
LRCLK
SCLK
SDI
SDO



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