TSL2581, TSL2583

LIGHT-TO-DIGITAL CONVERTER

TAOS134A − JULY 2012

15

The LUMENOLOGY

r Company

r

r

Copyright

E 2012, TAOS Inc.

www.taosinc.com

ID Register (12h)

The ID register provides the value for both the part number and silicon revision number for that part number.

It is a read-only register whose value never changes.

Table 11. ID Register

6

75

4

REVNO

2

31

0

PARTNO

Address

12h

Reset

− −

Bit :

FIELD

BITS

DESCRIPTION

PARTNO

7:4

Part Number Identification: field value 1001b

REVNO

3:0

Revision number identification

ADC Channel Data Registers (14h − 17h)

The ADC channel data are expressed as 16-bit values spread across two registers. The ADC channel 0 data

registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of

channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC

value of channel 1. All channel data registers are read-only and default to 00h on power up.

Table 12. ADC Channel Data Registers

REGISTER

ADDRESS

BITS

DESCRIPTION

DATA0LOW

14h

7:0

ADC channel 0 lower byte

DATA0HIGH

15h

7:0

ADC channel 0 upper byte

DATA1LOW

16h

7:0

ADC channel 1 lower byte

DATA1HIGH

17h

7:0

ADC channel 1 upper byte

The upper byte data registers can only be read following a read to the corresponding lower byte register. When

the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a

subsequent read to the upper byte. The upper register will read the correct value even if additional ADC

integration cycles end between the reading of the lower and upper registers.

NOTE: The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as

the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction

Manual Integration Timer Registers (18h − 19h)

The MANUAL INTEGRATION TIMER registers provide the number of cycles in 10.9

μs increments that

occurred during a manual start/stop integration period. The timer is expressed as a 16-bit value across two

registers. See CONTROL and TIMING Registers for further instructions in configuring a manual integration.

The maximum time that can be derived without an overflow is 714.3 ms.

Table 13.

6

75

4

2

31

0

TIMER

Address

18h 19h

Reset

00h

Bit :

REGISTER

ADDRESS

BITS

DESCRIPTION

TIMERLOW

18h

7:0

Manual Integration Timer lower byte

TIMERHIGH

19h

7:0

Manual Integration Timer upper byte