ATMEGA161-4AI datasheet(98/134 Pages) ATMEL

98 / 134 page

ATmega161(L)

Addressing the FLASH During Self-programming

The Z pointer is used to address the SPM commands.

Z15:Z14 always ignored

Z13:Z7

page select, for page erase, page write

Z6:Z1

word select, for filling temp buffer (must be zero during page write operation)

should be zero for all SPM commands, byte select for the LPM instruction.

The only operation that does not use the Z pointer is Setting the Boot Loader Lock Bits. The content of the Z pointer is

ignored and will have no effect on the operation.

Note that the page erase and page write operation is addressed independently. Therefore it is of major importance that the

Boot Loader software addresses the same page in both the page erase and page write operation.

The LPM instruction does also use the Z pointer to store the address. Since this instruction does address the FLASH byte

by byte, also the LSB (bit Z0) of the Z pointer is used. See page 16 for a detailed description.

Accidental writing into Flash program by the SPM instruction is prevented by setting up a "SPM enable time window". All

accesses are executed by first setting I/O bits, and then executing SPM within four clock cycles. The I/O register that con-

trols the SPM accesses is defined as follows:

Store Program Memory Control Register – SPMCR

The Store Program Memory Control Register contains the control bits needed to control the programming of the FLASH

from internal code execution.

• Bit 7..4 - Res: Reserved Bits

These bits are reserved bits in the ATmega161 and always read as zero.

• Bit 3 - BLBSET: Boot Lock Bit set

If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according

to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will auto-clear upon comple-

tion of lock bit set, or if no SPM instruction is executed within four clock cycles. The CPU is halted during lock bit setting.

Only a chip erase can clear the Lock Bits.

An LPM instruction within four cycles after BLBSET and SPMEN are set in the SPMCR register, will put either the Lock-bits

or the Fuse-bits (depending od the Z0 in the Z-pointer) into the destination register. See “Reading the Fuse- and Lock Bits

from Software” on page 99 for details.

• Bit 2 - PGWRT: Page write

If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the

data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0

are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire page write operation.

• Bit 1 - PGERS: Page Erase

If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The

page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear

upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the

entire page erase operation.

Bit

14131211

$1F ($1F)

Z15

Z14

Z13

Z12

Z11

Z10

$1E ($1E)

543

210

Bit

543

210

$37 ($57)

BLBSET

PGWRT

PGERS

SPMEN

SPMCR

Read/Write

R/W

Initial value

ATMEGA161-4AI Datasheet(PDF) 98 Page - ATMEL Corporation

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