ATMEGA161-4AI datasheet(21/134 Pages) ATMEL

21 / 134 page

ATmega161(L)

Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers $00 to $1F only.

The I/O and peripherals control registers are explained in the following sections.

Status Register – SREG

The AVR status register – SREG – at I/O space location $3F ($5F) is defined as:

• Bit 7 - I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is

then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are

enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has

occurred, and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6 - T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A

bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a

• Bit 5 - H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed

information.

• Bit 4 - S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-

tion Set Description for detailed information.

• Bit 3 - V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for

detailed information.

• Bit 2 - N: Negative Flag

The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set

Description for detailed information.

• Bit 1 - Z: Zero Flag

The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description

for detailed information.

• Bit 0 - C: Carry Flag

The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed

information.

Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from

an interrupt routine. This must be handled by software.

Bit

543

210

$3F ($5F)

SREG

Read/Write

R/W

Initial value

ATMEGA161-4AI Datasheet(PDF) 21 Page - ATMEL Corporation

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