5-2

FAST AND LS TTL DATA

SN54/74LS164

LOGIC DIAGRAM

Q6

Q7

A

B

Q0

Q1

Q3

Q2

Q5

Q4

MR

CP

D

Q

CD

D

Q

CD

D

Q

CD

D

Q

CD

D

Q

CD

D

Q

CD

D

Q

CD

D

Q

CD

6

3

4

5

11

12

10

13

VCC = PIN 14

GND = PIN 7

= PIN NUMBERS

1

2

8

9

FUNCTIONAL DESCRIPTION

The LS164 is an edge-triggered 8-bit shift register with seri-

al data entry and an output from each of the eight stages. Data

is entered serially through one of two inputs (A or B); either of

these inputs can be used as an active HIGH Enable for data

entry through the other input. An unused input must be tied

HIGH, or both inputs connected together.

Each LOW-to-HIGH transition on the Clock (CP) input shifts

data one place to the right and enters into Q0 the logical AND

of the two data inputs (A

•B) that existed before the rising clock

edge. A LOW level on the Master Reset (MR) input overrides

all other inputs and clears the register asynchronously, forcing

all Q outputs LOW.

MODE SELECT — TRUTH TABLE

OPERATING

MODE

INPUTS

OUTPUTS

MODE

MR

A

B

Q0

Q1–Q7

Reset (Clear)

L

X

X

L

L – L

H

I

I

L

q0 – q6

Shift

H

I

h

L

q0 – q6

H

h

I

L

q0 – q6

H

h

h

H

q0 – q6

L (l) = LOW Voltage Levels

H (h) = HIGH Voltage Levels

X = Don’t Care

qn = Lower case letters indicate the state of the referenced input or output one

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

TA

Operating Ambient Temperature Range

54

74

– 55

0

25

25

125

70

°C

IOH

Output Current — High

54, 74

– 0.4

mA

IOL

Output Current — Low

54

74

4.0

8.0

mA