®

ISO113

7

FIGURE 2b. Gain Setting.

FIGURE 2a. Gain Adjust.

V

21

IN

22

1k

Ω

R

1

11

10

9

R

2

2k

Ω

V

OUT

V

21

IN

22

11

10

9

Sense

V

OUT

R

2

R

1

Gain = 1 + (R

dictate location of the adjustment potentiometer on the other

side of the barrier from the position shown in Figure 2a, the

Gains greater than 1 may be obtained by using the circuit of

Figure 2b. Note that the effect of input referred errors will be

multiplied at the output in proportion to the increase in gain.

Also, the small-signal bandwidth will be decreased in in-

verse proportion to the increase in gain. In most instances, a

precision gain block at the input of the isolation amplifier

will provide better overall performance.

This circuit may be applied to Signal Com1. With the values

shown,

±15V supplies and unity gain, the circuit will pro-

vide

±150mV adjustment range and 0.25mV resolution with

a typical trim potentiometer. The output will have some

sensitivity to power supply variations. For a

±100mV trim,

power supply sensitivity is 8mV/V at the output.

11

10

9

Sense

V

OUT

400

Ω

4.7nF

V

21

IN

22

FIGURE 4. Ripple Reduction.

MULTICHANNEL SYNCHRONIZATION

Synchronization of multiple ISO113s can be accomplished

by connecting pin 3 of each device to an external TTL level

oscillator, as shown in Figure 7. The PWS750-1 oscillator is

convenient because its nominal synchronizing output fre-

quency is 1.6MHz, resulting in a 800kHz carrier in the

ISO113 (its nominal unsynchronized value). The open col-

lector output typically switches 7.5mA to a 0.2V low level

so that the external pull up resistor can be chosen for

different pull-up voltages as shown in Figure 7. The number

of channels synchronized by one PWS750-1 is determined

by the total capacitance of the sync voltage conductors. They

must be less than 1000pF to ensure TTL level switching at

800kHz. At higher frequencies the capacitance must be

proportionally lower.

Customers can supply their own TTL level synchronization

logic, provided the frequency is between 1.2MHz and 2MHz,

and the duty cycle is greater than 25%.

Single or multichannel synchronization with reduced power

dissipation for applications requiring less than

±15mA from

and Enable pin (1) with the TTL oscillator as shown in

Figure 5.

+V

CC1

1M

Ω

10k

Ω

Signal Com 1

100k

Ω

or +V

CC2

–V

OPTIONAL OUTPUT FILTER

Figure 4 shows an optional output ripple filter that reduces

the 800kHz ripple voltage to <5mVp-p without compromis-

ing DC performance. The small signal bandwidth is ex-

tended above 30kHz as a result of this compensation.

TTL Oscillation

23

ISO

12

3

15 14 13

16

113

External

Load

<15mA

12

+V

CC1

I

ISOLATION BARRIER VOLTAGE

The typical performance of the ISO113 under conditions of

barrier voltage stress is indicated in the first two perform-

ance curves—Recommended Range of Isolation Voltage

and IMR/ Leakage vs Frequency. At low barrier modulation

FIGURE 5. Reduced Power Dissipation.