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Data Sheet

AD7903

Rev. A | Page 17 of 28

VOLTAGE REFERENCE INPUT

The AD7903 voltage reference input, REF, has a dynamic input

impedance and must therefore be driven by a low impedance

source with efficient decoupling between the REFx and GND

pins, as explained in the Layout section.

When REF is driven by a very low impedance source (for

example, a reference buffer using the AD8031 or the AD8605),

a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate

for optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For instance, a 22 µF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR43x reference.

If desired, a reference decoupling capacitor with values as small

as 2.2 µF can be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value ceramic

decoupling capacitor (for example, 100 nF) between the REFx

and GND pins.

POWER SUPPLY

The AD7903 uses two power supply pins per ADC: a core supply

(VDDx) and a digital input/output interface supply (VIOx).

VIOx allows direct interface with any logic between 1.8 V and

5.5 V. To reduce the number of supplies needed, VIOx and VDDx

can be tied together. The AD7903 is independent of power supply

sequencing between VIOx and VDDx. Additionally, it is very

insensitive to power supply variations over a wide frequency

range, as shown in Figure 37.

Figure 37. PSRR vs. Frequency

For optimum performance, ensure that VDDx is roughly half of

REFx, the voltage reference input. For example, if REFx is 5.0 V,

set VDDx to 2.5 V (±5%).

The AD7903 powers down automatically at the end of each

conversion phase; therefore, the power scales linearly with the

sampling rate. This makes the part ideal for low sampling rates

(of even a few hertz) and low battery-powered applications.

Figure 38. Operating Currents per ADC vs. Sampling Rate

DIGITAL INTERFACE

Although the AD7903 has a reduced number of pins, it offers

flexibility in its serial interface modes.

When in CS mode, the AD7903 is compatible with SPI, QSPI,

digital hosts, and DSPs. In this mode, the AD7903 can use either

a 3-wire or 4-wire interface. A 3-wire interface using the CNVx,

SCKx, and SDOx signals minimizes wiring connections useful,

for instance, in isolated applications. A 4-wire interface using

the SDIx, CNVx, SCKx, and SDOx signals allows CNVx, which

initiates the conversions, to be independent of the readback

timing (SDIx). This is useful in low jitter sampling or

simultaneous sampling applications.

When in chain mode, the AD7903 provides a daisy-chain feature

using the SDIx input for cascading multiple ADCs on a single

data line similar to a shift register. With the AD7903 housing

two ADCs in one package, chain mode can be utilized to

acquire data from both ADCs while using only one set of 4-wire

user interface signals.

The mode in which the device operates depends on the SDIx

level when the CNVx rising edge occurs. CS mode is selected if

SDIx is high, and chain mode is selected if SDIx is low. The

SDIx hold time is such that when SDIx and CNVx are connected

together, chain mode is always selected.

In either mode, the AD7903 offers the option of forcing a start

bit in front of the data bits. This start bit can be used as a busy

signal indicator to interrupt the digital host and trigger the data

reading. Otherwise, without a busy indicator, the user must time

out the maximum conversion time prior to readback.

The busy indicator feature is enabled as follows:

•

In CS mode if CNVx or SDIx is low when the ADC

conversion ends (see Figure 42 and Figure 46).

•

In chain mode if SCKx is high during the CNVx rising

edge (see Figure 50).

10k

100k

FREQUENCY (Hz)

0.1

0.01

0.001

100000

SAMPLING RATE (SPS)

10000

1000000

IREF

IVDD

IVIO

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