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AD7690 Datasheet(PDF) 24 Page - Analog Devices

Part # AD7690
Description  Dual Differential 16-Bit, 1 MSPS PulSAR ADC 12.0 mW in QSOP
PDF  29 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7690 Datasheet(HTML) 24 Page - Analog Devices

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Data Sheet
AD7903
Rev. A | Page 23 of 28
Chain Mode with Busy Indicator
Chain mode with a busy indicator can also be used to daisy-
chain both ADCs within an AD7903 on a 3-wire serial interface
while providing a busy indicator. This feature is useful for reducing
component count and wiring connections, for example, in isolated
multiconverter applications or for systems with limited interfacing
capacity. Data readback is analogous to clocking a shift register.
See Figure 49 for a connection diagram example using three
AD7903 ADCs. The corresponding timing is shown in Figure 50.
When SDIx and CNVx are low, SDOx is driven low. With SCKx
high, a rising edge on CNVx initiates a conversion, selects chain
mode, and enables the busy indicator feature. In this mode, CNVx
is held high during the conversion phase and the subsequent data
readback. When all ADCs in the chain have completed their
conversions, the SDOx pin of the ADC closest to the digital host
(see the ADC labeled ADCx in the AD7903 B box in Figure 49)
is driven high. This transition on SDOx can be used as a busy
indicator to trigger the data readback controlled by the digital host.
The AD7903 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are clocked out,
MSB first, by subsequent SCKx falling edges. For each ADC,
SDIx feeds the input of the internal shift register and is clocked
by the SCKx falling edge. Each ADC in the chain outputs its
data MSB first, and 16 × N + 1 clocks are required to read back
the N ADCs. Although the rising edge can be used to capture the
data, a digital host using the SCKx falling edge allows a faster
reading rate and, consequently, more ADCs in the chain,
provided that the digital host has an acceptable hold time.
Figure 49. Chain Mode with Busy Indicator Connection Diagram
Figure 50. Chain Mode with Busy Indicator Serial Interface Timing
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7903
SDIxB
SDOxB
CNVx
SCKx
AD7903
AD7903 A
AD7903 B
SDI1A
SDO1A
CNVx
SCKx
IRQ
AD7903
SDI2A
SDO2A
CNVx
ADCx
ADC1
ADC2
SCKx
NOTES
1. DASHED LINE DENOTED ADCs ARE WITHIN A GIVEN PACKAGE.
2. SDI1A AND SDO1A REFER TO THE SDI1 AND SDO1 PINS IN ADC1 IN THE FIRST AD7903 OF THE CHAIN (AD7903 A).
SDI2A AND SDO2A REFER TO THE SDI2 AND SDO2 PINS IN ADC2 OF AD7903 A. LIKEWISE, SDIxB AND SDOxB REFER
TO THE SDIx AND SDOx PINS IN BOTH ADC1 AND ADC2 OF THE SECOND AD7903 IN THE CHAIN (AD7903 B)
tCONV
tCYC
tSSDISCK
tSCKH
tSCK
tHSDISCK
tACQ
tDSDOSDI
tDSDOSDI
tDSDODSI
ACQUISITION
tSSCKCNV
ACQUISITION
tSCKL
CONVERSION
tHSCKCNV
SCKx
CNVx = SDI1A
SDO1A =SDI2A
SDO2A =SDIxB
SDOxB
tEN
DA115 DA114 DA113
DA215 DA214
DA213
DBx15 DBx14
DBx13
DA21DA20DA115 DA114
DA11DA10
DBx1DBx0DA215
DA214
DA10
DA11
DA20
DA21DA114
DA115
DA11DA10
tHSDO
12
3
15
16
17
4
18
19
31
32
3334
35
4748
49
tDSDO
tDSDOSDI
tDSDOSDI



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