THS4281DBVT datasheet(21/37 Pages) NSC

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THS4281

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SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009

Power-Supply Decoupling Techniques and

cause unintentional band limiting. To reduce

Recommendations

unwanted capacitance, a window around the

signal I/O pins should be opened in all of the

Power-supply decoupling is a critical aspect of any

ground and power planes around those pins.

high-performance

amplifier

design.

Careful

Otherwise, ground and power planes should be

decoupling provides higher quality ac performance.

unbroken elsewhere on the board.

The following guidelines ensure the highest level of

2. Minimize the distance (< 0.1 inch) from the

performance.

power-supply pins to high-frequency, 0.1-

μF

1. Place decoupling capacitors as close to the

decoupling capacitors. Avoid narrow power and

power-supply inputs as possible, with the goal of

ground

traces

minimize

inductance.

The

minimizing the inductance.

power-supply

connections

should

always

2. Placement priority should put the smallest valued

decoupled as described above.

capacitors closest to the device.

3. Careful selection and placement of external

3. Use of solid power and ground planes is

components

preserves

the

high-frequency

recommended to reduce the inductance along

performance of the THS4281. Resistors should

power-supply return current paths (with the

be a low reactance type. Surface-mount resistors

exception of the areas underneath the input and

work best and allow a tighter overall layout.

output pins as noted below).

Metal-film, axial-lead resistors can also provide

good high-frequency performance. Again, keep

4. A bulk decoupling capacitor is recommended (6.8

the leads and PCB trace length as short as

μF to 22 μF) within 1 inch, and a ceramic (0.1 μF)

possible. Never use wire-wound type resistors in

within 0.1 inch of the power input pins.

a high-frequency application. Because the output

pin and inverting input pin are the most sensitive

NOTE

to parasitic capacitance, always position the

feedback and series output resistor, if any, as

The bulk capacitor may be

close as possible to the output pin. Other network

shared by other op amps.

components,

such

noninverting

input

termination resistors, should also be placed close

BOARD LAYOUT

to the package. Excessively high resistor values

Achieving

optimum

performance

with

can create significant phase lag that can degrade

high-frequency amplifier like the THS4281 requires

performance. Keep resistor values as low as

careful attention to board layout parasitics and

possible,

consistent

with

load-driving

external component types. See the EVM layout

considerations. It is suggested that a good

figures (Figure 78 to Figure 81) in the Design Tools

starting point for design is to set the Rf to 2 kΩ for

section.

low-gain, noninverting applications. Doing this

automatically keeps the resistor noise terms

Recommendations that optimize performance include:

reasonable and minimizes the effect of parasitic

1. Minimize parasitic capacitance to any ac

capacitance.

ground for all of the signal I/O pins. Parasitic

capacitance on the output and inverting input pins

can cause instability and on the noninverting

input, it can react with the source impedance to

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