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ICS953002 Datasheet(PDF) 22 Page - Integrated Circuit Systems |
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ICS953002 Datasheet(HTML) 22 Page - Integrated Circuit Systems |
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22 / 35 page  22 Integrated Circuit Systems, Inc. ICS953002 0924—11/18/09 I 2C Table: Device Control Register Bit 7 FS Source Frequency H/W IIC Select RW 0 Bit 6 Reserved Reserved RW 1 Bit 5 ROD Reset On Demand RW 0 Bit 4 FS4 Freq/Div Sel Bit 4 RW latch Bit 3 FS3 Freq/Div Sel Bit 3 RW latch Bit 2 FSL2 Freq/Div Sel Bit 2 RW latch Bit 1 FSL1 Freq/Div Sel Bit 1 RW latch Bit 0 FSL0 Freq/Div Sel Bit 0 RW latch I 2C Table: Device Control Register Bit 7 SS_EN1 PLL1 Spread Enable RW 1 Bit 6 SS_EN2 PLL2 Spread Enable RW 1 Bit 5 M/N Enable bit M/N Programming Enable bit RW 0 Bit 4 CPUFS4 PLL1 VCO Sel b4 RW X Bit 3 CPUFS3 PLL1 VCO Sel b3 RW X Bit 2 CPUFS2 PLL1 VCO Sel b2 RW 0 Bit 1 CPUFS1 PLL1 VCO Sel b1 RW 0 Bit 0 CPUFS0 PLL1 VCO Sel b0 RW 0 B1b[4:3] = 00 is invalid I 2C Table: Output Control Register Bit 7 REF0 Output Control RW 1 Bit 6 REF1 Output Control RW 1 Bit 5 PCICLK0 Output Control RW 1 Bit 4 PCICLK1 Output Control RW 1 Bit 3 PCICLK2 Output Control RW 1 Bit 2 PCICLK3 Output Control RW 1 Bit 1 PCICLK4 Output Control RW 1 Bit 0 PCICLK5 Output Control RW 1 I 2C Table: Output Control Register Bit 7 48MHz Output Control RW 1 Bit 6 24_48MHz Output Control RW 1 Bit 5 3V66_2 Output Control RW 1 Bit 4 3V66_1 Output Control RW 1 Bit 3 3V66_0 Output Control RW 1 Bit 2 - SEL24_48MHz Output Select RW Latch Bit 1 ITP_EN Output Select RW Latch Bit 0 Mode 0 Output Select RW Latch Enable Disable Enable Enable Disable Disable Disable Disable Enable Enable CPU_STOP/PCI_P CIEX_STOP CPUCLKT/C2 48MHz 24MHz - - - - - PWD - Name Control Function Type 0 - - - Byte 3 - - - Name 1 Enable Disable Disable Name Type Control Function Type PWD 1 01 Latch Inputs OFF Enable - - - PWD PWD - Byte 1 Pin # - - - - - Pin # - - Name - - - Byte 2 Pin # - - - Type Byte 0 Pin # - Control Function Control Function IIC ON ON -- Disable Enable See Table 1b: PLL2 AGP/PCI Frequency Selection Table OFF 0 Disable Disable PCIEXCLKT/C5 Disable 1 PCIEXCLKT/C0 Enable Disable Enable Enable Enable Disable Disable Disable Enable See Table 1a: PLL1 Rom VCO Frequency Selection Table 0 Enable - Enable |
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