CS22220 datasheet(15/34 Pages) CIRRUS

15 / 34 page

CS22220 Wireless PCMCIA Controller

15 of 34

DS557PP2

Rev. 3.0

www.cirrus.com

PC Card Interface

The PC Card interface is PCMCIA 2.1 fully compliant interface. The following provides detail pin

description.

PCD[15:0]

Bi-directional

Data lines. The data bus contains the data to be written on a write cycle

and the read return data on a read cycle.

PCA[10:0]

Input

Address lines. Signal PCA[10:0] are address bus input lines. PCA10 is

the most significant bit. During memory word access mode, A0 is not

used. During I/O word access cycle, A0 must be negated.

nPCE[2:1]

Input

Card enable. These lines are active low input signals. nPCE1 enables

even numbered addresses and nPCE2 enables odd numbered

addresses.

nPOE

Input

Output enable. This signal is used to gate memory read data from

memory card.

nPCWE

Input

Write enable. This is active low input signal is used for strobing memory

write data into the memory card.

nPCREG

Input

Attribute memory select. Assertion of this signal indicates the access is

limited to attribute memory and to I/O space. Attribute memory is a

separate accessed section of card memory and is generally used to

record card capacity and other configuration and attribute information.

nPCIREQ

Output

Interrupt request. This signal is asserted to indicate to the host system

that a PC card device requires host software service.

nPCSTSCHG

Output

PC card status changed – Not supported. This pin is used as a mode

strap pin. When asserted during reset, PC CARD I/F uses the big endian

protocol; otherwise pulled low (Default), it uses the little endian protocol.

CS22220 Datasheet(PDF) 15 Page - Cirrus Logic

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