CS43122 datasheet(16/28 Pages) CIRRUS

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CS43122

MCLK

Master Clock (Input) - The master clock frequency must be either 256x, 384x,

512x or 768x the input sample rate in Operational Mode 0; either 128x, 192x 256x

or 384x the input sample rate in Operational Mode 1 ; or 64x, 96x 128x or 192x the

input sample rate in Operational Mode 2 . Tables 4-6 illustrate the standard audio

sample rates and the required master clock frequencies.

SCLK

Serial Clock

(Input) - Clocks individual bits of serial data into the SDATA pin. The

required relationship between the Left/Right clock, serial clock and serial data is

defined by either the Mode Control Byte in Control Port Mode or the M0 - M4 pins

in Hardware Mode. The options are detailed in Figures 20-23.

LRCK

Left/Right Clock

(Input) - The Left/Right clock determines which channel is cur-

rently being input on the serial audio data input, SDATA. The frequency of the

Left/Right clock must be at the input sample rate. Audio samples in Left/Right

sample pairs will be simultaneously output from the digital-to-analog converter

whereas Right/Left pairs will exhibit a one sample period difference. The required

relationship between the Left/Right clock, serial clock and serial data is defined by

the Mode Control Byte and the options are detailed in Figures 20-23.

SDATA

Serial Audio Data

(Input) - Two’s complement MSB-first serial data is input on

this pin. The data is clocked into SDATA via the serial clock and the channel is

determined by the Left/Right clock. The required relationship between the

Left/Right clock, serial clock and serial data is defined by the Mode Control Byte

and the options are detailed inin Figures 20-23.

Sample Rate

(kHz)

MCLK (MHz)

256x

384x

512x

768x

8.1920

12.2880

16.3840

24.5760

44.1

11.2896

16.9344

22.5792

33.8688

12.2880

18.4320

24.5760

36.8640

Table 1. Operational Mode 0 (16 to 55 kHz sample rates) Common Clock

Frequencies

Sample Rate

(kHz)

MCLK (MHz)

128x

192x

256x

384x

6.1440

8.1920

12.2880

16.3840

8.1920

12.2880

16.3840

24.5760

88.2

11.2896

16.9344

22.5792

33.8688

12.2880

18.4320

24.5760

36.8640

Table 2. Operational Mode 1 (45 to 105 kHz sample rates) Common Clock

Frequencies

Sample Rate

(kHz)

MCLK (MHz)

64x

96x

128x

192x

176.4

11.2896

16.9344

22.5792

33.8688

192

12.2880

18.4320

24.5760

36.8640

Table 3. Operational Mode 2 (95 to 200 kHz sample rates) Common Clock

Frequencies

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