DS241PP5

23

CS4610/11

CrystalClear™ SoundFusion™ PCI Audio Accelerator

Note: A ‘#’ sign suffix on a pin names indicates an active-low signal.

PCI Interface

AD[31:0] - Address/Data Bus, I/O

(M) pins 88-92, 95-97, 2-6, 9-11, 28-29, 32-37, 41-48

(Q) pins 116-120, 123-125, 2-6, 9-11, 36-37, 40-45, 49-56

These pins form the multiplexed address / data bus for the PCI interface.

C/BE[3:0]# - Command Type / Byte Enables, I/O

(M) pins 98, 14, 27, 38; (Q) pins 126, 14, 35, 46

These four pins are the multiplexed command / byte enables for the PCI interface. During the

address phase of a transaction, these pins indicate cycle type. During the data phases of a

transaction, active low byte enable information for the current data phase is indicated. These

pins are inputs during slave operation and they are outputs during bus mastering operation.

PAR - Parity, I/O

(M) pin 26; (Q) pin 34

The Parity pin indicates even parity across AD[31:0] and C_BE[3:0] for both address and data

phases. The signal is delayed one PCI clock from either the address or data phase for which

parity is generated.

FRAME# - Cycle Frame, I/O - Active Low

(M) pin 15; (Q) pin 15

FRAME# is driven by the current PCI bus master to indicate the beginning and duration of a

transaction.

IRDY# - Initiator Ready, I/O

(M) pin 16; (Q) pin 24

IRDY# is driven by the current PCI bus master to indicate that as the initiator it is ready to

transmit or receive data (complete the current data phase).

TRDY# - Target Ready, I/O

(M) pin 17; (Q) pin 25

TRDY# is driven by the current PCI bus target to indicate that as the target device it is ready to

transmit or receive data (complete the current data phase).

STOP# - Transition Stop, I/O

(M) pin 23; (Q) pin 31

STOP# is driven active by the current PCI bus target to indicate a request to the master to stop

the current transaction.

IDSEL - Initialize Device Select, Input

(M) pin 99; (Q) pin 127

IDSEL is used as a chip select during PCI configuration read and write cycles.