W147G
PRELIMINARY
3
Overview
The W147G is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/APICDIV is a dual purpose l/O pin. Upon power-up the
pin acts as a logic input. If the pin is strapped to a LOW state
externally, APIC clock outputs will run divide synchronously at
half PCI clock speed. If it is pulled HIGH, APIC clock will run
synchronous to PCI clocks. An external 10-k
Ω strapping resis-
tor should be used. Figure 1 shows a suggested method for
strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1 outlines the device functions selectable through
SEL0:1. Specific outputs available at each pin is detailed in
Table 2 below. The SEL0 pin requires a 220
Ω pull-up resistor
to 3.3V for the W147G to sense the maximum host bus fre-
quency of the processor and configure itself accordingly.
Notes:
1.
APIC clock frequency determined by the strap option on the REF/APICDIV input pin.
2.
Provided for board level “bed of nails” testing.
3.
“Normal” mode of operation.
4.
TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5.
Required for DC output impedance verification.
6.
Range of reference frequency allowed is: min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W147G
VDD
Clock Load
10 k
Ω
Output
Buffer
(Load Option 1)
10k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. CK Whitney Truth Table
SEL1
SEL0
CPU
SDRAM
3V66
PCI
48MHz
REF
APIC[1]
Notes
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2
0
1
TCLK/2
TCLK/2
TCLK/3
TCLK/6
TCLK/2
TCLK
TCLK/6
4, 5
1
0
66 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
3, 6, 7
1
1
100 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
3, 6, 7
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