ICS810251I Data Sheet

VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR

ICS810251AGI REVISION B OCTOBER 5, 2012

2

©2012 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1

PLL_SEL

Input

Pullup

When logic HIGH, the VCXO-PLL is enabled. When LOW, the VCXO-PLL is in

bypass mode. LVCMOS/LVTTL interface levels.

2, 9, 12

GND

Power

Power supply ground.

3

Reserved

Reserved

Reserved pin. Do not connect.

4

Q

Output

Single-ended clock output. LVCMOS/ LVTTL interface levels.

Power

Output power supply pin.

6

OE

Input

Pullup

Output enable pin for Q output. LVCMOS/LVTTL interface levels.

Power

Analog supply pin.

8, 15

Power

Core supply pins.

10,

11

XTAL_OUT,

XTAL_IN

Input

VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

13, 14

LF0, LF1

Analog

Input/

Output

Loop filter connection node pins.

16

CLK_IN

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Power Dissipation Capacitance

8

pF

5

pF

Input Pullup Resistor

51

k



51

k



Output Impedance

15



20

