DS2152L datasheet(25/94 Pages) DALLAS

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DS2152

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CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)

(MSB)

(LSB)

ESMDM

ESR

RLOSF

RSMS

PDE

ECUS

TLOOP

SYMBOL

POSITION

NAME AND DESCRIPTION

ESMDM

CCR3.7

Elastic Store Minimum Delay Mode. See Section 10.3 for

details.

0 = elastic stores operate at full two-frame depth

1 = elastic stores operate at 32-bit depth

ESR

CCR3.6

Elastic Store Reset. Setting this bit from a 0 to a 1 will force the

elastic stores to a known depth. Should be toggled after

RSYSCLK and TSYSCLK have been applied and are stable.

Must be cleared and set again for a subsequent reset.

RLOSF

CCR3.5

Function of the RLOS/LOTC Output.

0 = Receive Loss of Sync (RLOS)

1 = Loss of Transmit Clock (LOTC)

RSMS

CCR3.4

RSYNC Multiframe Skip Control. Useful in framing format

conversions from D4 to ESF. This function is not available when

the receive side elastic store is enabled.

0 = RSYNC will output a pulse at every multiframe

1 = RSYNC will output a pulse at every other multiframe

note: for this bit to have any affect, the RSYNC must be set to

output multiframe pulses (RCR2.4=1 and RCR2.3=0).

PDE

CCR3.3

Pulse Density Enforcer Enable.

0 = disable transmit pulse density enforcer

1 = enable transmit pulse density enforcer

ECUS

CCR3.2

Error Counter Update Select. See Section 5 for details.

0 = update error counters once a second

1 = update error counters every 42 ms (333 frames)

TLOOP

CCR3.1

Transmit Loop Code Enable. See Section 12 for details.

0 = transmit data normally

1 = replace normal transmitted data with repeating code as

defined in TCD register

CCR3.0

Not Assigned. Must be set to 0 when written.

Pulse Density Enforcer

The SCT always examines both the transmit and receive data streams for violations of the following rules

which are required by ANSI T1.403:

no more than 15 consecutive 0s

at least N 1s in each and every time window of 8 x (N +1) bits where N = 1 through 23

Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits

respectively. When the CCR3.3 is set to 1, the DS2152 will force the transmitted stream to meet this

requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should

be set to 0 since B8ZS encoded data streams cannot violate the pulse density requirements.

DS2152L Datasheet(PDF) 25 Page - Dallas Semiconductor

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