DS2175

3 of 12

PIN Description Table 1

PIN

SYMBOL

TYPE

DESCRIPTION

1

RCLKSEL

I

2

RCLK

I

Receive Clock. 1.544 or 2.048 MHz data clock.

3

RSER

I

Receive Serial Data. Sampled on falling edge of RCLK.

4

RMSYNC

I

Receive Multifram Sync. Rising edge establishes receive side

frame and multiframe boundaries.

5

FSD

O

Frame Slip Directions. State indicates direction of last slip;

latched on slip occurrence.

6

SLIP

O

Frame Slip. Active low, open collector output. Held low for 65

SYSCLK cycles when a slip occurs.

7

ALN

I

Align. Recenters buffer on next system side frame boundary when

forced low; negative edge-triggered.

8

–

Signal Ground. 0.0 volts.

9

SCLKSEL

I

10

I

11

SCHCLK

O

System Channel Clock. Transitions high on channel boundaries;

useful for serial to parallel conversion of channel data.

12

SFSYNC

I

System Frame Sync. Rising edge establishes system side frame

boundaries.

13

SMSYNC

O

System Multiframe Sync. Slip-compensated multiframe output;

used with RMSYNC to monitor depth of store real time.

14

SSER

O

System Serial Data. Updated on rising edge of SYSCLK.

15

SYSCLK

I

System Clock. 1.544 or 2.048 MHz data clock.

16

–

Positive Supply. 5.0 volts.

PCM BUFFER

The DS2175 utilizes a 2–frame buffer to synchronize in-coming PCM data to the system backplane clock.

Buffer depth is mode–dependent; 2.048 MHz to 2.048 MHz applications utilize 64 bytes of buffer

memory, while all other modes are supported by 48 bytes. The buffer samples data at RSER on the falling

edge of RCLK. Output data appears at SSER and is updated on the rising edge of SYSCLK. The buffer

depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is completely

emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always occur on frame

boundaries.

DATA FORMAT

Data is presented to, and output from, the elastic store in a “framed” format. A rising edge at RMSYNC

and SFSYNC establishes frame boundaries for the receive and system sides. North American (T1) frames

contain 24 data channels of 8 bits each and an F–bit (193 bits total). European (CEPT) frames contain 32

data channels (256 bits). The frame rate of both systems is 8 KHz. RMSYNC and SFSYNC do not

require a pulse at every frame boundary; if desired, they may be pulsed once to establish frame alignment.

Internal counters will then maintain the frame alignment and may be reinforced by the next rising edge at

RMSYNC and/or SFSYNC.