ZADCS0882/0842/0822

8-Bit, 300ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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Layout

To achieve optimum conversion performance care must be taken in design and layout of the application

board. It is highly recommended to use printed circuit boards instead of wire wrap designs and to establish a

single point star connection ground system towards AGND (see Figure 19).

For optimal noise performance the star point should be located very close to the AGND pin of the converter.

The ground return to the power supply should be as short as possible and low impedance.

All other analog ground points of external circuitry that is related to the A/D converter as well as the DGND pin

of the device should be connected to this ground point too. Any other digital ground system should be kept

apart as far as possible and connect on the power supply point only.

Analog and digital signal domains should also be separated as well as possible and analog input signals

should be shielded by AGND ground planes from electromagnetic interferences. Four-layer PCB boards that

allow smaller vertical distances between the ground plane and the shielded signals do generally show a better

performance than two-layer boards.

The sampling phase is the most critical portion of the overall conversion timing for signal distortion. If possible,

the switching of any high power devices or nearby digital logic should be avoided during the sampling phase

of the converter.

Current consumption vs. Sample Rate

1

10

100

1000

10000

1

10

100

1000

Sample Rate (ksps)

Figure 18: Supply Current versus Sampling Rate

Figure 19: Optimal Power-Supply Grounding System

COM

DGND

D

Other

Digital

CircuitryVDD

VDD1

Optional

R = 10Ω

ZADCS08x2

Family

GND

VDD2

(+2.7 … +5.25V)

The fully differential internal architecture of the ZADCS08x2 family ensures very good suppression of power

supply noise. Nevertheless, the SAR architecture is generally sensitive to glitches or sudden changes of the

power supply that occur shortly before the latching of the comparator output. It is therefore recommended to

bypass the power supply connection very close to the device with capacitors of 0.1µF (ceramic) and >1µF

(electrolytic). In case of a noisy supply, an additional series resistor of 5 to 10 ohms can be used to low-pass

filter the supply voltage. The reference voltage should always be bypassed with capacitors of 0.1µF (ceramic)

current of about 100µA is drawn through the VREF pin that could cause a noticeable voltage drop across the

resistance.