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3.2.6 Phase 2 Clock (CLK02N)

Output. CLK02N is used by the MA17502 Control Unit

(CU) in conjunction with CLKPCN to synchronize

microinstruction transmission on the M Bus to the

MAS281 machine cycle.

CLK02N cycles associated with MAS281 external

memory or l/O bus transactions are a minimum of five

OSC cycles in duration and are extended when wait

states are inserted via the RDYN input.

The high-to-low transition of CLK02N places the

upper 20 bits of a microinstruction on the external M Bus.

Wait states extend the trailing (based on SYNCN high-to-

low beginning the machine cycle) low state of CLK02N.

When PAUSEN or HLDAKN is low, CLK02N is held high.

CLK02N cycles associated with internal MAS281

operations are either five or six OSC cycles in duration.

Six OSC cycles are required for machine cycles

associated with microcode branches or with the

execution of internally (Interrupt Unit) decoded XlO

commands. Five OSC cycles are used for all other

internal operations, e.g., register to register transfers,

ALU functions, etc.

[NOTE: For MAS281s operating at high OSC

frequencies, the Interrupt Unit logic that creates IRDYN

may cause a wait state to be inserted during execution of

internal XlO commands. This would result in a CLK02N

cycle of seven OSC cycles duration.]

3.3 BUS CONTROL

This group of signals is provided to control Address/

Data (AD) bus transmissions (See Figure 4). The signals

indicate when address or data information is on the AD

Bus and what type of transaction is taking place during a

particular machine cycle.

3.3.1 Address Strobe (AS)

Output/Hi-z. AS high indicates that the Address/Data

(AD) Bus contains address information. The address

information is assured stable at the high-to-low transition

of this signal. ln this way, AS provides the necessary

control for a system Address Bus transparent latch

system interface.

The Interrupt Unit uses AS to extract the XlO

command information off the AD Bus for internally

decoded XlO commands, and the Memory Management

Unit/Block Protection Unit (MMU(BPU)) uses AS to

extract address information for memory management

and block protection functions, and to extract XlO

command information for MMU(BPU) decoded XlO

commands.

AS is placed in the high-impedance state during DMA

cycles by PAUSEN low and during the Hold state by

HLDAKN low. During internal non-AD Bus related CPU

operations, AS is held low for the entire machine cycle via

microcode control.

Figure 4: Typical MAS281/MA17504 System Interface

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