IO10PDB0V0 datasheet(186/197 Pages) MICROSEMI

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6- 4

R ev isio n 1 2

Revision 9

(continued)

The following note was added to Table 2-86 • SmartFusion CCC/PLL Specification in

regard to delay increments in programmable delay blocks (SAR 34816):

"When the CCC/PLL core is generated by Microsemi core generator software, not all

delay values of the specified delay increments are available. Refer to SmartGen

online help for more information."

2-63

Figure 2-36 • FIFO Read and Figure 2-37 • FIFO Write have been added (SAR

34851).

2-72

Information regarding the MSS resetting itself after IAP of the FPGA fabric was added

to the "Reprogramming the FPGA Fabric Using the Cortex-M3" section (SAR 37970).

4-8

Instructions for unused VCC33ADCx pins were revised in "Supply Pins" (SAR 41137).

5-1

Libero IDE was changed to Libero SoC throughout the document (SAR 40264).

N/A

Revision 8

(March 2012)

In the "Analog Front-End (AFE)" section, the resolution for the first-order sigma delta

DAC was corrected from 12-bit to "8-bit, 16-bit, or 24-bit." The same correction was

made in the "SmartFusion cSoC Family Product Table" (SAR 36541).

I, II

The "SmartFusion cSoC Family Product Table" was revised to break out the features

by package as well as device.

The table now indicates that only one SPI is available for the PQ208 package in

A2F200 and A2F500, and in the TQ144 package for A2F060 (SAR 33477).

The EMC address bus size has been corrected to 26 bits (SAR 35664).

The "SmartFusion cSoC Device Status" table was revised to change the CS288

package for A2F200 and A2F500 from preliminary to production status (SAR 37811).

III

TQ144 package information for A2F060 was added to the "Package I/Os: MSS +

FPGA I/Os" table, "SmartFusion cSoC Device Status" table, "Product Ordering

Codes", and "Temperature Grade Offerings" table (SAR 36246).

III, VI

Table 1 • SmartFusion cSoC Package Sizes Dimensions is new (SAR 31178).

III

The Halogen-Free Packaging code (H) was removed from the "Product Ordering

Codes" table (SAR 34017).

The "Specifying I/O States During Programming" section is new (SAR 34836).

1-3

The reference to guidelines for global spines and VersaTile rows, given in the "Global

Clock Dynamic Contribution—PCLOCK" section, was corrected to the "Device

Architecture" chapter in the SmartFusion FPGA Fabric User's Guide (SAR 34742).

2-15

The AC Loading figures in the "Single-Ended I/O Characteristics" section were

updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O

Software Settings" section (SAR 34891).

2-30,

2-24

The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34799):

"It uses a 5 V–tolerant input buffer and push-pull output buffer."

2-32

In the SRAM "Timing Characteristics" tables, reference was made to a new

application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs,

which covers these cases in detail (SAR 34874).

2-69

The note for Table 2-93 • Current Monitor Performance Specification was modified to

include the statement that the restriction on the TM pad being no greater than 10 mV

above the CM pad.is applicable only if current monitor is used (SAR 26373).

2-77

The unit "FR" in Table 2-96 • ABPS Performance Specifications and Table 2-98 •

Analog Sigma-Delta DAC, used to designate full-scale error, was changed to "FS"

and clarified with a table note (SAR 35342).

2-81,

2-84

Revision

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