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04/09/2009

10

iP2005CPbF

PD-60360

Internal Block Diagram

Figure 12 Internal Block Diagram

Pin Description

Pin Number

Pin Name

Description

1

Input voltage pin. Connect input capacitors close to this pin.

2

Voltage Switching Node – pin connection to the output inductor.

3

PGND

Power Ground

4

Supply voltage to internal circuitry.

5

PWM

TTL level input to MOSFET drivers. When PWM is HIGH, the Control

FET is on and the Sync FET is off. When PWM is LOW, the Sync FET

is on and the Control FET is off.

6

ENABLE

When set to logic level high, internal circuitry of the device is enabled.

When set to logic level low, the Control and Synchronous FETs are

turned off.

7,8

N/C

No Connection, can be left floating. (Note A)

Notes:

A. It is recommended to connect PIN 7 and 8 to PIN 1 on PCB to reduce thermal resistance.