AT25DF321A datasheet(18/53 Pages) ETC2

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3686F–DFLASH–1/2014

AT25DF321A

Protection Commands and Features

9.1

Write Enable

The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The

WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector

Lockdown State, Program OTP Security Register, or Write Status Register command can be executed. This makes the

issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously

executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these commands, then the command

will not be executed.

To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin

is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must be clocked into the

device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);

otherwise, the device will abort the operation and the state of the WEL bit will not change.

Figure 9-1. Write Enable

9.2

Write Disable

The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical "0" state.

With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector

Lockdown State, Program OTP Security Register, and Write Status Register commands will not be executed. Other conditions

can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register description.

To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin

is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the

device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);

otherwise, the device will abort the operation and the state of the WEL bit will not change.

SCK

MSB

00000110

OPCODE

HIGH-IMPEDANCE

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