AT25DF321A datasheet(4/53 Pages) ETC2

4 / 53 page

3686F–DFLASH–1/2014

AT25DF321A

Block Diagram

Figure 3-1. Block Diagram

Memory Array

To provide the greatest flexibility, the memory array of the AT25DF321A can be erased in four levels of granularity including

a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be

individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data

storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory Architecture

Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector.

Figure 2-1.

8-SOIC (Top View)

Figure 2-2.

8-UDFN (Top View)

Figure 2-3.

9-UBGA (Top View)

SO (SOI)

GND

VCC

HOLD

SCK

SI (SIO)

SCK

GND

VCC

HOLD

FLASH

MEMORY

ARRAY

Y-GATING

SCK

SO (SOI)

SI (SIO)

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

CONTROL AND

PROTECTION LOGIC

SRAM

DATA BUFFER

INTERFACE

CONTROL

AND

LOGIC

HOLD

SO (SOI)

GND

VCC

HOLD

SCK

SI (SIO)

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