AT45DB321E datasheet(44/73 Pages) ETC2

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AT45DB321E

8784F–DFLASH–11/2013

16.

Power-On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI

Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will

be required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) will be automatically selected on every falling

edge of CS by sampling the inactive clock state.

16.1 Initial Power-Up Timing Restrictions

During power-up, the device must not be accessed for at least the minimum tVCSL time after the supply voltage reaches

the minimum VCC level. While the device is being powered-up, the internal Power-On Reset (POR) circuitry keeps the

device in a reset mode until the supply voltage rises above the maximum POR threshold value (VPOR). During this time,

all operations are disabled and the device will not respond to any commands. After power-up, the device will be in the

standby mode.

If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be

started until the supply voltage reaches the minimum VCC level and an internal device delay has elapsed. This delay will

be a maximum time of tPUW.

Table 16-1. Power-Up Timing

Figure 16-1. Power-Up Timing

Symbol

Parameter

Min

Max

Units

tVCSL

Minimum VCC to Chip Select Low Time

μs

tPUW

Power-Up Device Delay Before Program or Erase Allowed

VPOR

Power-On Reset (POR) Voltage

1.5

2.2

Program/Erase Operations Permitted

Read Operation Permitted

VCC

VCC (min)

VPOR (max)

VPOR (min)

Time

Do Not Attempt

Device Access

During this Time

tPUW

tVCSL

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