AT45DB321E datasheet(45/73 Pages) ETC2

45 / 73 page

AT45DB321E

8784F–DFLASH–11/2013

17.

System Considerations

The serial interface is controlled by the Serial Clock (SCK), Serial Input (SI), and Chip Select (CS) pins. These signals

must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted

as multiple edges and cause improper operation of the device. PCB traces must be kept to a minimum distance or

appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to

provide filtering against noise glitches.

As system complexity continues to increase, voltage regulation is becoming more important. A key element of any

voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash

devices occurs during the programming and erasing operations. The supply voltage regulator needs to be able to supply

this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system

noise, current starvation during programming or erasing can lead to improper operation and possible data corruption.

AT45DB321E Datasheet(PDF) 45 Page - List of Unclassifed Manufacturers