IO196NPB3 datasheet(201/210 Pages) MICROSEMI

201 / 210 page

ProASIC3 Flash Family FPGAs

Re vi s i on 15

5 - 5

Revision 5 (Aug 2008)

DC and Switching

Characteristics v1.3

TJ, Maximum Junction Temperature, was changed to 100° from 110º in the

"Thermal Characteristics" section and EQ 1. The calculated result of Maximum

Power Allowed has thus changed to 1.463 W from 1.951 W.

2-5

Values for the A3P015 device were added to Table 2-7 • Quiescent Supply

Current Characteristics.

2-6

Values for the A3P015 device were added to Table 2-14 • Different Components

Contributing to Dynamic Power Consumption in ProASIC3 Devices. PAC14 was

removed. Table 2-15 • Different Components Contributing to the Static Power

Consumption in ProASIC3 Devices is new.

2-10, 2-11

The "PLL Contribution—PPLL" section was updated to change the PPLL formula

from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT.

2-13

Both fall and rise values were included for tDDRISUD and tDDRIHD in Table 2-102 •

Input DDR Propagation Delays.

2-77

Table 2-107 • A3P015 Global Resource is new.

2-85

The typical value for Delay Increments in Programmable Delay Blocks was

changed from 160 to 200 in Table 2-115 • ProASIC3 CCC/PLL Specification.

2-89

Revision 4 (Jun 2008)

DC and Switching

Characteristics v1.2

Table note references were added to Table 2-2 • Recommended Operating

Conditions 1, and the order of the table notes was changed.

2-2

The title for Table 2-4 • Overshoot and Undershoot Limits 1 was modified to

remove "as measured on quiet I/Os." Table note 1 was revised to remove

"estimated SSO density over cycles." Table note 2 was revised to remove "refers

only to overshoot/undershoot limits for simultaneous switching I/Os.

2-2

The "Power per I/O Pin" section was updated to include 3 additional tables

pertaining to input buffer power and output buffer power.

2-6

Table 2-29 • I/O Output Buffer Maximum Resistances 1 was revised to include

values for 3.3 V PCI/PCI-X.

2-26

Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels was

updated.

2-65

Revision 3 (Jun 2008)

Packaging v1.3

Pin numbers were added to the "QN68 – Bottom View" package diagram. Note 2

was added below the diagram.

4-3

The "QN132 – Bottom View" package diagram was updated to include D1 to D4.

In addition, note 1 was changed from top view to bottom view, and note 2 is new.

4-6

Revision 2 (Feb 2008)

Product Brief v1.0

This document was divided into two sections and given a version number, starting

at v1.0. The first section of the document includes features, benefits, ordering

information, and temperature and speed grade offerings. The second section is a

device family overview.

N/A

This document was updated to include A3P015 device information. QN68 is a

new package that was added because it is offered in the A3P015. The following

sections were updated:

"Features and Benefits"

"ProASIC3 Ordering Information"

"Temperature Grade Offerings"

"ProASIC3 Flash Family FPGAs"

"A3P015 and A3P030" note

Introduction and Overview (NA)

N/A

Revision

Changes

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