L1DMPPA21 datasheet(9/222 Pages) TI1

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OMAP-L137

www.ti.com

SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014

Table 3-1. Characteristics of the OMAP-L137 Processor (continued)

HARDWARE FEATURES

OMAP-L137

674x DSP at 375 MHz(1.2V) or 456 MHz (1.3V)

CPU Frequency

MHz

ARM926 at 375 MHz(1.2V) or 456 MHz (1.3V)

Core (V)

1.2V / 1.3V

Voltage

I/O (V)

3.3 V / 1.8 V (1.8 V for USB only)

Package

17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB)

Product Preview (PP),

Advance Information

375 MHz Versions -PD

Product Status(1)

(AI),

456 MHz Version - PD

or Production Data

(PD)

(1)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

3.2

Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both

the C64x+ and C67x+ DSP families.

3.3

ARM Subsystem

The ARM Subsystem includes the following features:

•

ARM926EJ-S RISC processor

•

ARMv5TEJ (32/16-bit) instruction set

•

Little endian

•

System Control Co-Processor 15 (CP15)

•

MMU

•

16KB Instruction cache

•

16KB Data cache

•

Write Buffer

•

Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

•

ARM Interrupt controller

3.3.1

ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of

ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications

where full memory management, high performance, low die size, and low power are all important. The

ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to

trade off between high performance and high code density. Specifically, the ARM926EJ-S processor

supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,

providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code

overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a

complete high performance subsystem, including:

•

ARM926EJ -S integer core

•

CP15 system control coprocessor

•

Memory Management Unit (MMU)

•

Separate instruction and data caches

•

Write buffer

Device Overview

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