MB40C950VPFQ datasheet(4/17 Pages) FUJITSU

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MB40C950V

s PIN DESCRIPTION

Pin No.

Symbol

I/O

Description

LQFP64

QFP64

4 to 13

15 to 24

29 to 38

5 to 14

18 to 27

29 to 38

R0 to R9

G0 to G9

B0 to B9

Data signal incoming terminal for Rch, Gch and Bch

LSB: R0, G0, B0

MSB: R9, G9,B9

RCLK

GCLK

BCLK

Clock signal incoming terminal for Rch, Gch and Bch

Power saving signal incoming terminal. Power saving

enabled for High

DVDD

—

Digital power supply terminal

54, 60

55, 61

AVDD

—

Analog power supply terminal

DVSS

—

Digital ground terminal

56, 58

57, 59

AVSS

—

Analog ground terminal

RVRIN

GVRIN

BVRIN

Rererence voltage incoming terminal for Rch, Gch and

Bch

RIREF

GIREF

BIREF

—

Reference resistor connection terminal for Rch, Gch and

Bch

—

Connect >0.1

µF capacitor to the AVSS terminal

RVB

GVB

BVB

—

Connect >0.1

µF capacitor to the AVDD terminal

ROUT

GOUT

BOUT

Analog signal output terminals for Rch, Gch and Bch

2 to 3

25 to 28

39, 45

46, 50

3 to 4

15 to 17

39 to 42

N.C.

—

Not connected. To be left open.

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